The Institute of Circuit Technology

Section 1 - Editor's Introduction

Welcome to the latest edition of our Journal. Our first paper explores how modern solder masks exceed the traditional design rules for insulation and creepage. Our second paper seeks to explain and clarify the key metallurgical and process factors that determine the reliability of stacked microvias. Finally we have an article on the prospects of resolving the worldwide shortage of electronics grade glass fabric and the actions that are in progress. There are some interesting topics in the sections on members and Industry news. 

Please feel free to forward this Journal to colleagues who may be interested. They can subscribe using the link above to receive future editions.

Section 2 - Calendar of Events

 Alun Morgan
Technical Director

Note: Registration is now open for our Annual Symposium. Tuesday October 6th, Coventry, UK. Free to members and £35.00 for non-members. Read more...

 Section 3
Modern Solder Masks Challenge Traditional Creepage Design Rules
M. Vogt, A. Brunko, M.R. Meier, H. Schweigart, L. Henneken, M. Schleicher, D. Schucht, N. Kaminski

Editor’s Introduction
As electric vehicles, renewable energy systems and industrial power electronics move towards ever higher operating voltages, PCB designers face increasing pressure to reduce board size whilst maintaining electrical safety and long-term reliability. Existing creepage and insulation requirements are largely based on standards developed around materials and manufacturing processes that are now several decades old.

This paper examines whether modern solder mask technologies can deliver significantly better insulation performance than these long-established design assumptions. Using accelerated high-voltage and humidity testing, the authors compare four commercially available solder mask systems and show that material selection has a far greater influence on insulation performance than conductor geometry. Particularly impressive results were achieved with one of the inkjet-applied solder mask systems.

The findings suggest that advances in solder mask materials could eventually support reductions in creepage distances without compromising reliability. Whilst further validation and standards development will be required, the work provides compelling evidence that modern solder mask technology deserves greater consideration in the design of high-voltage PCBs for automotive, power conversion and industrial applications.
— ICT Editor

Background
Printed circuit boards (PCBs) have formed the foundation of the electronics industry for decades. Extensive reliability research and continuous manufacturing improvements have made them highly dependable components, with well-established design rules and industry standards ensuring consistent performance across a wide range of applications. These standards, however, were developed for the operating conditions and materials available at the time. As operating voltages continue to increase whilst demand for higher power density remains strong, those long-standing assumptions are being challenged. Traditional methods of increasing creepage distance, such as incorporating slots or cut-outs into the PCB, consume valuable board area and can reduce mechanical strength.

To address electrical safety, the European Low Voltage Directive (LVD, 2014/35/EU) requires products to comply with harmonised standards that provide a presumption of conformity throughout the European Union. These standards draw upon guidance from organisations including IEC, ISO, CEN, CENELEC and ETSI. However, differences remain between some international standards. For example, the US IPC-2221B standard and the European IEC standards specify different creepage distance requirements, raising important questions about the most appropriate design rules for future high-voltage, high-power applications.

These challenges are particularly relevant in the automotive sector. The transition to electric vehicles has dramatically increased the expected service life of electronic systems. Whereas electronics in conventional internal combustion vehicles typically operated for around 6,000 hours, components used in modern electric vehicles may be expected to remain reliable for up to 130,000 hours because of extended operating periods associated with battery charging, standby operation and continuous connectivity.

At the same time, manufacturers face increasing pressure to improve sustainability, reduce product size and control costs. Achieving these objectives will require advances in insulation materials as well as future revisions to design standards that fully reflect the capabilities of modern PCB technologies.

Considerable research has already been undertaken into humidity-related reliability mechanisms, including Electrochemical Migration (ECM), Conductive Anodic Filament (CAF) formation and the Anodic Migration Phenomenon (AMP). Building on this body of knowledge, the present study focuses on the long-term insulation performance of solder mask materials applied to the outer layers of printed circuit boards under high-humidity conditions. By improving understanding of these degradation mechanisms, the work aims to support future PCB designs that achieve higher power density or reduced board size without compromising long-term reliability.

Experimental Procedure

HV-H3TRB test method
High Voltage–High Humidity–High Temperature Reverse Bias (HV-H3TRB) testing has become an established method for evaluating the long-term insulation performance of electronic materials under accelerated environmental conditions. Originally developed for power semiconductor qualification, the technique provides a realistic means of assessing humidity-related degradation without introducing many of the failure mechanisms associated with more aggressive Highly Accelerated Stress Tests (HAST).

For PCB applications, climatic conditions are particularly important because different combinations of temperature and humidity can accelerate different degradation mechanisms. Whilst power semiconductor testing is commonly carried out at 85 °C/85% relative humidity, automotive PCB testing typically uses 65 °C/93% relative humidity. Both conditions were included within the Design of Experiments (DoE) to assess their influence on insulation performance.

The climatic test profile is illustrated in Figure 1. Test specimens were conditioned in a climate chamber for approximately 24 hours before a 1 kV DC bias was applied. Following each test period, the chamber was returned to 25 °C and 50% relative humidity before electrical measurements and visual inspections were carried out.

Figure 1. HV-H3TRB environmental test profile showing temperature, relative humidity and the period during which the 1 kV bias voltage was applied.

A purpose-built multi-channel test system continuously monitored leakage current from 64 test channels throughout the programme. Individual channels were automatically isolated if an overcurrent condition was detected, preventing damage to neighbouring test specimens and allowing testing to continue. Leakage current was measured using transimpedance amplifiers connected to a commercial data acquisition system. A test voltage of 1 kV DC was selected to represent emerging 850 V-class electric vehicle applications whilst remaining compatible with laboratory safety requirements.

PCB Test Coupons
PCB test coupons were manufactured to evaluate the influence of conductor geometry, solder mask material and copper thickness on long-term insulation performance. Four conductor geometries representative of common PCB layouts were incorporated into the test design (Figure 2): a conventional zig-zag pattern (A), a standard comb structure (B), a sinusoidal pattern (C) designed to reduce electric field concentration, and a second comb structure (D) with increased conductor spacing and no solder mask passivation over the copper. The final configuration was included to determine whether exposed copper could inhibit dendrite growth.

Figure 2. Layout of the test boards: A zig-zag structure, B comb and C sinusoidal, all with 2.325 mm spacing and D comb with 3.2 mm spacing.

The principal test structures (A, B and C) all used a conductor spacing of 2.325 mm, consistent with creepage distances defined in IPC-2221 and IEC 60664-1. Additional variations were intentionally included to investigate whether modern solder mask materials could support further miniaturisation in future high-voltage PCB designs.

The test boards were manufactured using a high-performance FR-4 laminate based on a phenol-novolac resin system with a glass transition temperature (Tg) of 170 °C, together with controlled thermal expansion characteristics and a Comparative Tracking Index (CTI) corresponding to PLC-3.

To assess the influence of copper thickness, test coupons were produced using both 35 μm (1 oz) and 105 μm (3 oz) base copper. These values represent typical automotive PCB constructions. The thicker copper was expected to provide reduced insulation performance because of its effect on solder mask edge coverage and leakage current paths.

Figure 3 illustrates a typical result from the test programme. As exposure time increased, insulation resistance gradually decreased in susceptible materials. Optical examination confirmed that this degradation corresponded with the formation and growth of conductive dendrites.

Figure 3. Typical insulation resistance during HV-H3TRB testing, showing the progressive reduction in resistance over time together with representative optical images illustrating dendrite formation under different test conditions.

Solder Mask Materials
Four solder mask systems were evaluated. The reference material, A1 (Rezept 733), had previously been investigated ^[3] and was developed for automotive applications. F1 (Rezept 330) was selected because of its lower temperature rating and lower degree of cross-linking. J1 and J2 represented emerging inkjet-applied solder mask technologies, introducing material classes that had not previously been investigated.

A1 was applied by silk-screen printing, using a double application on the 105 μm copper boards to achieve edge coverage greater than 10 μm. F1 was applied using a similar process. J1 was an inkjet-applied solder mask without fillers, providing a thinner coating whilst still achieving 10 μm edge coverage. J2 was a thicker inkjet-applied solder mask achieving approximately 20 μm edge coverage.

These variables produced a Design of Experiments (DoE) matrix comprising 32 test variants. Each variant was evaluated using two test specimens, giving a total of 64 test channels distributed across 16 boards. The DUTs were initially tested for 168 hours, visually inspected for dendrite growth, and then returned to the climate chamber for further test periods, with the programme concluding after 2,000 hours.

Optical analysis
Optical examination was carried out using transmitted light before each test run and again after 2,000 hours (or after 1,000 hours for the 85 °C/85% RH test because of a scheduled maintenance stop). Optical examination confirmed that reductions in insulation resistance were directly associated with degradation of the DUT and the formation of AMP dendrites. Representative examples are shown in Figure 3.

Comparison of the intermediate inspection at 1,000 hours with the final inspection at 2,000 hours suggests that electrical stabilisation occurs after the initial formation of AMP dendrites.

Statistical evaluation
To quantify the influence of the experimental variables, insulation resistance data were extracted from the measurement curves at selected sampling intervals and analysed using Design of Experiments (DoE) techniques. Statistical evaluation confirmed that insulation resistance was influenced by several factors, including solder mask material, climate, copper thickness and test duration.

A polynomial model was developed using the Minitab statistical package, incorporating solder mask material, base copper thickness, conductor geometry, climate and test duration. The model achieved an adjusted R² value of 0.86, indicating good agreement with the experimental data. The principal effects are summarised in Figure 4.

Figure 4. Main effect plot of insulation resistance data from DoE analysis; fitted means from median.

Of all the variables investigated, solder mask material had by far the greatest influence on insulation resistance (Figure 4). The lowest values were recorded for the F1 solder mask, an epoxy-acrylate polymer containing a high level of fillers. The inkjet-applied material Jc produced the highest insulation resistance, whilst A1 showed intermediate performance.

The poorer performance of F1 is attributed to its lower degree of cross-linking and lower temperature rating. Under prolonged exposure to humidity and high voltage, water absorbed into the solder mask promotes electrolysis, generating hydrogen gas and hydroxide ions. The resulting alkaline environment gradually degrades the polymer network. Materials with higher filler content or greater ionic contamination accelerate this process by increasing conductivity within the polymer, whereas higher cross-link density and lower ionic contamination improve long-term insulation performance.

The excellent performance of the inkjet-applied material Jc is thought to result from its optimised acrylate cross-linking and very low filler content. Material A1 also performed well, probably because of its higher temperature rating and the use of cleaner raw materials. Subsequent chemical analysis supported these conclusions and highlighted the importance of ionic contamination in determining long-term insulation performance.

Figure 4 also shows a progressive reduction in insulation resistance with increasing test duration, indicating continued hydrolytic degradation of the polymer. Climatic conditions also had a significant influence, with the greatest deterioration occurring at 85 °C/85% relative humidity and the least at 65 °C/85% relative humidity, consistent with Arrhenius behaviour.

Copper thickness was also found to influence insulation resistance. Test coupons with 105 μm copper consistently produced lower insulation resistance than those with 35 μm copper because the thicker copper provides a larger cross-sectional path for leakage currents through the insulation.

No failures associated with inadequate solder mask edge coverage were observed during the test programme. Conductor geometry also affected insulation resistance, although its influence was much smaller than that of solder mask material. The conventional comb structures (B and D) produced the lowest insulation resistance, whereas the rounded geometries (A and C), which reduce electric field concentration, consistently gave higher values.

Chemical analysis
Chemical analysis provided further insight into the degradation mechanisms responsible for the differences observed during electrical testing.

Ion chromatography, carried out in accordance with IPC TM 650 2.3.28, showed that the F1 solder mask, which exhibited the highest leakage current throughout the HV-H3TRB programme, also exhibited the highest ionic load.

Infrared microscopy was used to compare solder mask samples before and after HV-H3TRB testing (Figure 5). All materials showed evidence of polymer ageing, particularly the inkjet-applied materials. Samples exposed to 85 °C/85% relative humidity exhibited the greatest degradation, indicating that
temperature is the dominant driver of oxidative ageing.

Figure 5. Infrared spectra of inkjet solder mask samples before (black) and after HV-H3TRB stress (blue, green, red).

Interestingly, despite showing the greatest evidence of polymer ageing, the inkjet-applied solder masks delivered the best electrical insulation performance throughout the HV-H3TRB tests. This apparent contradiction suggests that conventional polymer qualification methods may not fully predict long-term performance under combined high-voltage and high-humidity conditions. The findings therefore support the development of validation procedures better suited to modern high-voltage PCB insulation systems.

Conclusions
The HV-H3TRB test method proved to be an effective means of evaluating creepage distance and solder mask performance on the outer layers of printed circuit boards. The tests consistently triggered the Anodic Migration Phenomenon (AMP) within the polymer insulation layer, providing a realistic means of assessing long-term insulation behaviour. As AMP shares many characteristics with the well-known Conductive Anodic Filament (CAF) mechanism, existing CAF modelling approaches may also be applicable to AMP.

The results showed that PCB geometry, including conductor profile and edge shape, had only a limited influence on leakage current, although geometry did affect dendrite growth. By comparison, solder mask material, climatic conditions and test duration had the greatest influence on long-term insulation performance, with conductor geometry playing a secondary role.

Despite conductor spacings being smaller than those specified by current standards, no catastrophic failures occurred during the 2,000-hour test programme under any of the climatic conditions investigated. These findings suggest that modern solder mask materials can provide significantly greater insulation capability than is assumed in existing creepage design rules. Whilst further validation is required, the results provide encouraging evidence that future standards may be able to take advantage of advances in modern insulation materials.

Further work is required to investigate the influence of conductor spacing, operating voltage and fast switching transients in greater detail. These studies should provide the basis for developing lifetime models that more accurately predict the long-term behaviour of high-voltage PCB insulation systems.

Adapted for publication in the ICT Journal from an original open-access paper published in Microelectronics Reliability.

Practical Implications for PCB Manufacturers
The results of this study demonstrate how advances in modern solder mask materials can significantly improve the electrical insulation performance of printed circuit boards operating in high-voltage, high-humidity environments. Whilst further validation is required before existing design standards can be revised, several practical conclusions can already be drawn.

• Material selection is critical. The choice of solder mask material had a far greater influence on insulation resistance than conductor geometry or track profile, emphasising the importance of selecting solder mask systems specifically designed for high-voltage applications.
  
  
• Modern inkjet-applied solder masks performed exceptionally well. The inkjet materials evaluated in this study consistently achieved the highest insulation resistance, suggesting that newer solder mask technologies may offer significant advantages for future high-voltage PCB designs.
  
  
• Current creepage requirements may be conservative for modern materials. Despite conductor spacings being below those recommended by existing standards, none of the PCB test coupons suffered catastrophic failure during 2,000 hours of accelerated humidity and high-voltage testing. These findings may contribute to future revisions of creepage distance requirements as additional validation data becomes available.
  
  
• Long-term environmental testing remains essential. The work demonstrates the value of accelerated HV-H3TRB testing for assessing solder mask reliability and identifying degradation mechanisms that may not be apparent during conventional qualification testing.
  
  
• Further research is still required. The influence of conductor spacing, operating voltage and fast switching transients requires additional investigation before these findings can be translated directly into design standards or production guidelines.

About this Article
This article is based on the following open-access publication.
Original Authors: M. Vogt, A. Brunko, M.R. Meier, H. Schweigart, L. Henneken, M. Schleicher, D. Schucht and N. Kaminski.
Original Publication:
"Solder mask as a reliable insulation layer on printed circuit boards – different layouts and materials under humidity and high voltage."
Microelectronics Reliability, Volume 169 (2025), Article 115743.
DOI: https:// doi.org/10.1016 /j.microrel.2025.115743
The original paper is published under the Creative Commons Attribution (CC BY 4.0) licence.
This ICT Journal version has been adapted for length, readability and house style. The technical content, experimental results and conclusions remain those of the original authors.
Readers wishing to consult the complete paper, including the full reference list, acknowledgements and supporting information, should refer to the original publication using the DOI above.

Section 4
Reliability starts at the Cu/Cu/Cu microvia junction
Kuldip Johal, Roger Massey, Dr. Tobias Bernhard
MKS Atotech

Editors Introduction
The rapid growth of artificial intelligence (AI), high-performance computing and advanced electronic systems is placing unprecedented demands on printed circuit boards, package substrates and high-density interconnect (HDI) technology. Increasing power density, higher signal speeds and greater interconnect complexity are driving the adoption of stacked blind microvias and other advanced interconnection structures that must maintain reliable electrical and mechanical performance throughout the product lifetime. This paper examines some of the key metallurgical and process factors that determine the reliability of these increasingly critical interconnections. – ICT Editor

Introduction

Even if a stacked blind microvia passes inspection, it can still fail if copper recrystallization stalls at one of the Cu/Cu/Cu interfaces, or if nanovoids and impurity-rich initiation layers predetermine a crack path. Evidence from metallography, Transmission Electron Microscopy with Energy-Dispersive X-ray spectroscopy (TEM/EDX), and hot-oil reliability testing shows that: ^[1] epitaxial (“bottom-up”) recrystallization improves lifetime and reduces interface definition; ^[2] the early stages of electroless and electrolytic initiation are decisive; and ^[3] Normalized Crack Length (NCL) provides a rapid, quantitative screening method that correlates with cycles-to-failure in thermo-mechanical testing.

1. Relevance and system context

AI accelerators with high power density and large package footprints amplify thermo-mechanical loading across substrates and boards. The interconnect hierarchy, extending from the semiconductor die and High Bandwidth Memory (HBM) through to the PCB, shifts reliability sensitivity “down” into copper junctions in the package substrate and board.

1.1. Where reliability fails - The Cu/Cu/Cu junctions

The demand for higher bandwidth, lower latency, and increased compute density driven by AI accelerators and their surrounding infrastructure raises power delivery and signal integrity requirements that cascade into package substrates and PCBs. These requirements push designs toward fine-feature routing and more complex hybrid constructions, such as high-aspect-ratio multilayers and High Density Interconnect (HDI) build-ups. Due to high power density and large package footprints, thermo-mechanical loading increases across substrates and boards, while rising interconnect density creates more copper interfaces. As a result, the interconnect hierarchy shifts reliability sensitivity down into the copper-to-copper junctions within the package substrate and board. This makes reliability increasingly dependent on the integrity of these junctions below the silicon stack.

Figure 1: Schematic: Cu filled blind microvia (BMV) with typical layer thicknesses (target pad, Pd seed, electroless Cu, galvanic Cu).

Figure 2: Typical failure of a BMV at the target pad (a) and SEM showing target pad electroless Cu – electrolytic Cu structure (b)

2. Problem statement and failure physics

2.1. Recrystallization mode determines joint life

After plating, copper evolves from a fine-grained, metastable state toward a recrystallized microstructure. Two outcomes are observed: (i) epitaxial (“bottom-up”) recrystallization, where the electroless Cu inherits the pad texture and electrolytic Cu continues it, reducing distinct interfaces; and (ii) nonepitaxial (“top-down”) recrystallization, where each layer recrystallizes independently, leaving a persistent interface that can act as a crack pathway.

The preferred case is bottom-up recrystallization, where post-plating crystallization proceeds via grain-boundary motion and grain coarsening. The recrystallization front initiates at the bottom of the via and progresses upward, so each newly plated layer crystallizes coherently with the underlying copper. However, if diffusion is impeded at an interface, recrystallization proceeds by local seeding and grain growth within each layer. This produces a persistent boundary — the “top-down” case.

Manufacturing outcomes are not always binary. For example, if the target pad–electroless interface is clean, but the electroless–electrolytic interface is contaminated by additive incorporation, the epitaxial alignment point can shift upward. This results in mixed-mode recrystallization.

2.2. Nanovoids and impurity segregation

Nanovoids with diameters below 10 nm may be invisible to conventional FIB/SEM (Focused Ion Beam/Scanning Electron Microscopy) yet materially change interface cohesion and recrystallization behaviour. High-resolution TEM/HAADF (High-Angle Annular Dark Field) with EDX enables allocation of voided regions to specific layers and interfaces, distinguishing voids embedded within recrystallized grains from voids at interfaces that suppress epitaxy.

3. Nanovoid formation mechanisms at the Cu/Cu/Cu junction

An extensive TEM/EDX field study involving more than 400 investigations identified several types of nanovoid formation at the Cu/Cu/Cu junction. These differ in when they occur, the interface affected and their influence on recrystallisation. The critical finding is that voids at the electroless/electrolytic copper interface that suppress epitaxial growth present the greatest reliability risk.

Nanovoid formation can originate at several stages of the metallisation process. Palladium agglomerates introduced during activation can contribute to thermally induced voiding, while pre-existing copper oxides and inadequate solution exchange during electroless copper initiation can produce aligned voids or nanoporous regions. Surface roughness and electroless copper chemistry can also encourage nodule-associated voiding. During electrolytic copper initiation, impurity incorporation can produce nanoscale voids and, where impurities accumulate at the electroless/electrolytic interface, inhibit grain-boundary migration and continuity of recrystallisation.

The practical significance is therefore not simply whether nanovoids are present, but where they occur and whether they interrupt epitaxial recrystallisation across the Cu/Cu/Cu junction. Table 1 summarises the principal nanovoid classifications, their likely origins and their implications for reliability.

Table 1: Condensed nanovoid classification and reliability implications.

Figure 5: Summary of nanovoid types, root causes and impact on recrystallisation (classification overview).

 4. Predictive microstructure screening - Normalized Crack Length (NCL)

Not all microvias that appear satisfactory under conventional inspection will perform equally well in service. Normalized Crack Length (NCL) provides a way of assessing the microstructure of the copper interface and estimating its susceptibility to cracking. In simple terms, a higher NCL indicates a more favourable microstructure and a potentially more reliable joint, allowing different plating processes to be compared before lengthy reliability testing is completed.

NCL provides a microstructure-based metric for comparing joints that may look similar by conventional inspection. The method estimates a likely crack path through the interface, guided by grain boundaries (best visualized using Electron Backscatter Diffraction (EBSD)).

Figure 6: Example microstructures and associated NCL values (screening resolution). 

4.1. Correlation with thermo-mechanical testing

In example datasets, small NCL differences between process legs correspond to large differences in hot oil cycles-to-failure, supporting NCL as a high-sensitivity discriminator during development and troubleshooting.

4.2. AI packaging workflow - Using NCL to triage process options

NCL can be used during process development to compare different electroless and electrolytic copper combinations before committing to lengthy reliability testing. By identifying differences in microstructure at an early stage, less favourable process combinations can be screened out and the most promising options selected for further testing.

Figure 9: NCL performance is affected by electroless/electrolytic combinations.

5. Engineering controls – Linking process discipline to outcomes

Trends in advanced packaging include larger body sizes, finer pitches, and higher-temperature assembly profiles. At the same time, thermo-mechanical stress increases and failure sensitivity shifts from bulk copper to HDI/modified Semi-Additive Process (mSAP) microvia structures. The dominant limiter becomes the interfacial condition and early-growth metallurgy at the Cu/Cu/Cu junction (e.g., at stacked blind microvia bases). There, oxide, additive/conditioner residues, and micro-/nanovoid populations can cause cracking under cyclic strain. However, interface evolution and recrystallization can be actively controlled through disciplined interface cleanliness and early deposition engineering.

5.1. Control points across the Cu/Cu/Cu junction

The first lever is interface control: capture pads and via bottoms are kept free of oxide and residue (including desmear/conditioner films) by minimizing air breaks and queue time, as well as controlling contamination re-entry at transfer, rinse, and hold steps. Electroless Cu seeding is stabilized through disciplined chemistry and uniform hydrodynamics, while monitoring prevents bath drift, nonuniform coverage, and impurity uptake.

The second lever is early plating. The first 1–5 μm of electrolytic copper is treated as a high-risk nucleation regime. This regime is controlled via the balance of additives and halides, solution exchange, mass transport, and a defined current ramp/waveform. These controls suppress persistent interfacial boundaries and nanovoids. The thermal budget is managed to align with assembly and operating profiles and to limit adverse recrystallization and interface evolution.

5.2. Diagnostic contamination signatures

Although interfaces do not need to be completely free of impurities, they must be clean enough to prevent contamination levels that block grain-boundary diffusion and disrupt epitaxial growth. The main risk to reliability is localized enrichment that “suspends” epitaxy. In bottom-up/epitaxial cases, metallography and EDX typically reveal only the expected markers, such as nickel (Ni) from electroless Cu, plus low background signals of common elements, including carbon (C), nitrogen (N), sulfur (S), and chlorine (Cl), which do not hinder diffusion significantly.

By contrast, top-down/non-epitaxial cases often exhibit significant enrichment at the target pad-electroless interface, consistent with surface contamination present before electroless deposition. This enrichment includes elements such as Ni, Cl, bromine (Br), S, C, N, and oxygen (O). In particular, bromine enrichment may indicate epoxy resin systems and inadequate cleaning, while unusually high nickel, sulfur, chlorine, and nitrogen levels may indicate process-liquid entrapment.

6. Conclusion

Field and laboratory evidence indicates that there is no single “silver bullet” for ensuring the reliability of stacked blind microvias (BMVs). Robust performance comes from disciplined control of multiple interacting factors across cleaning, activation, electroless deposition, galvanic initiation, and thermal history. Critically, metallization risks should not be managed in isolation. Capture-pad condition, interface cleanliness, and early plating behavior can interact and increase sensitivity to failure at the Cu/Cu/Cu junction.

As AI-driven packaging continues to scale, reliability assurance must remain microstructure-aware and be applied as early as possible in process development. NCL screening provides a fast, quantitative method for ranking process windows, while TEM/EDX-based nanovoid and interface localization enables identification of root causes beyond routine inspection. Together with tightly controlled wet-process conditions, these methods support epitaxial continuity across interfaces. The next steps are to formalize reliability boundary conditions, use microstructure-based screening before lengthy thermal cycling, and apply targeted failure analysis to refine interface cleanliness and early deposition parameters. This can accelerate development cycles and expand robust manufacturing windows for advanced PCBs, package substrates, and hybrid bonding.

Practical Implications for PCB Manufacturers

For PCB manufacturers, the key message is that microvia reliability depends not only on achieving complete copper coverage and acceptable finished geometry, but also on controlling the condition of the interfaces during metallisation. Careful surface preparation, consistent electroless copper deposition and tightly controlled early electrolytic plating can reduce the risk of nanovoids and discontinuities that inhibit epitaxial recrystallisation. Microstructure-based techniques such as NCL can also provide an earlier indication of process robustness than conventional inspection alone. —Editor

References

^[1] Advanced packaging for AI - Reliability starts at the Cu/Cu/Cu microvia junction for i-Connect007 newsletter “Advanced packaging for AI” (April 26, MKS’ Atotech)

^[2] Nanovoid Formation at Cu/Cu/Cu Interconnections of Blind Microvias: A Field Study (first presented by MKS’ Atotech at IMAPS 2019)

^[3] A Review of Factors Effecting Crystallisation and Epitaxial Growth in Blind Micro Vias (first presented by MKS’ Atotech at IPC APEX 2026)

Go back to Contents

Section 5
Electronic E-Glass Fabric
Why capacity investment will not quickly end the shortage
Mark Goodwin Chief Operating Officer, Ventec International Group
August 2026

Executive summary
Adding electronic-grade glass-yarn capacity does not automatically solve the electronic-glass-fabric shortage. Yarn is only the first half of the process. It must also be woven on specialised equipment, heat cleaned, surface treated, inspected, qualified and brought to stable production yield before it becomes usable reinforcement for copper-clad laminate and PCB manufacture.
This creates a second, downstream constraint at precisely the point when fabric producers are redirecting capital, equipment and technical resources towards low-CTE, low-Dk/low-Df and ultra-thin products for AI infrastructure, high-performance computing, advanced packaging and very-high-speed networking. That investment is commercially rational, but it is also reducing the resources available for mainstream E-glass styles such as 7628, 2116, 1080 and 106.
The industry is responding. China Jushi, Kingboard, Fulltech, Nittobo and others have announced significant investments. However, the distinction between announced nameplate capacity and stable, qualified commercial output is critical. Construction, equipment delivery, commissioning, process ramp and customer qualification mean that many of the most important projects will not provide meaningful relief until the second half of 2027 or 2028.

1. The shortage is spreading into mainstream E-glass
Much of the industry discussion has focused on low-CTE T-glass and low-Dk/low-Df fabrics required for AI accelerators, IC package substrates and the next generation of high-speed network equipment.
That shortage is real. TrendForce estimates that Nittobo holds approximately 90% of the T-glass market and 60–70% of the NER-glass market. It does not expect meaningful new capacity to ease those constraints before mid-2027 at the earliest. ^[1]
The effect, however, is no longer confined to specialist products. Electronic-fabric manufacturers are increasingly directing yarn, looms, finishing capacity and technical resources towards:

• low-CTE glass for advanced packaging;
• low-Dk/low-Df glass for high-speed and low-loss laminates;
• ultra-thin fabrics for HDI and IC substrates; and
• higher-margin products supporting AI and high-performance computing.

This inevitably squeezes conventional E-glass. AI may be driving demand at the high end, but the reallocation of production resources is tightening availability across the much wider PCB market.
The most visible evidence is pricing. Fulltech announced a 30% increase for its E-glass fabrics from 1 July 2026, compared with 15% for its higher-performance FLD2 material. The company cited higher yarn, energy and logistics costs, but the scale of the E-glass increase also reflects the scarcity of mainstream electronic fabric. ^[2]
This matters because conventional constructions account for enormous volumes. A supply chain can be expanding its total fabric capacity while simultaneously making less of the standard styles on which the wider industrial, automotive and high-reliability PCB markets still depend.

2. China Jushi is making the largest visible investment
The largest confirmed capacity addition is China Jushi’s Huai’an complex in Jiangsu. Its first new line was ignited in March 2026 and was designed with annual nameplate capacity of 100,000 tonnes of electronic-grade glass yarn and 390 million metres of electronic glass fabric. ^[3–5]

Jushi describes this as the world’s largest single electronic-grade glass-fibre production line. The company subsequently announced a further investment of approximately US$653 million at Huai’an. ^[3]

An 18-month construction programme from May 2026 points towards completion around late 2027—not immediate market relief. Mechanical completion must then be followed by commissioning, process stabilisation, qualification and volume ramp.
Jushi sold 1.06 billion metres of electronic fabric during 2025 and estimates that it held 35–40% of the Chinese market. The expansion is clearly material, but much of its output will also serve China’s rapidly growing domestic CCL, PCB, AI and advanced-packaging industries. ^[3]
It should not therefore be assumed that every new metre of Chinese capacity will become freely available to the global merchant market.

3. The wider investment pipeline is substantial—but concentrated in Asia
Several other producers are investing, but the geographic pattern is unmistakable: practically all meaningful new electronic-fabric capacity is being added in China, Taiwan, Japan and Thailand.

 Kingboard’s investment underlines the move by vertically integrated laminate groups to secure more of their own upstream requirement. This can increase total industry capacity without producing a corresponding increase in freely traded supply. ^[6]
Fulltech’s Thailand project is strategically important because it follows the southward movement of CCL and PCB production into Southeast Asia. The project has received Thai investment approval and is targeted to begin contributing capacity during 2027. ^[7–9]
Nittobo is expanding specialist-glass capacity in Japan, but the timing again illustrates the lag between demand and supply. Its disclosed programme schedules production from the fourth quarter of fiscal 2026, followed by a gradual ramp rather than an immediate step-change. ^[10–11]
Grace Fabric Technology’s draft listing document provides a particularly clear view of the economics driving the market towards premium materials. Its 2025 revenue increased 40.3%, gross margin reached 35.1%, and low-CTE fabric sales volumes rose 131.1% in the first quarter of 2026 compared with the fourth quarter of 2025. ^[12]
Europe and North America retain some specialist glass production, but there is no visible regional investment wave capable of materially reducing their dependence on Asian electronic-fabric supply.
The geography of investment is also reshaping supply-chain optionality
The headline geography alone does not tell the full story. The more important issue is what type of capacity is being built in each location. The largest visible additions for conventional electronic-grade E-glass yarn and fabric are centred in China. By contrast, investment in Japan and Taiwan is increasingly directed towards T-glass, low-Dk/low-Df glass, low-CTE reinforcement and other specialist products serving advanced packaging and high-speed applications. Thailand adds a useful alternative fabric location, but it does not yet represent an independent, fully developed upstream ecosystem on the scale required by the global conventional CCL market. ^{[3, 7–11]}
This creates a strategic distinction between the geography of CCL production and the geography of its raw materials. Laminate treating and pressing capacity can move into Southeast Asia, Europe or North America, but that does not by itself create a non-Chinese upstream supply chain. Without parallel investment in conventional E-glass melting, filament forming, yarn preparation, weaving and finishing, the new CCL plant may still depend on Chinese yarn or fabric.
In practical terms, a large-scale ‘no China, no Taiwan’ supply chain upstream of CCL production is becoming extremely difficult—and for many standard electronic-glass constructions may be close to impossible. Taiwan and Japan remain strategically important sources of advanced glass, but they are not visibly building the volume of conventional E-glass needed to replace China. The current investment profile therefore increases, rather than reduces, the industry’s dependence on Chinese supply for mainstream E-glass, even as downstream manufacturing becomes more geographically diverse.

4. Weaving equipment has become part of the constraint
Electronic glass cloth is not produced on a generic textile loom with a simple change of yarn. The process requires air-jet looms and associated preparation equipment configured to handle brittle, low-elongation glass filaments. Warp tension, weft insertion, static control, filament damage, cleanliness and fabric geometry must all be tightly controlled.
Established equipment suppliers include Toyota Industries, Tsudakoma and Dornier, alongside specialist Chinese manufacturers such as Rifa and Haijia. Toyota and Tsudakoma remain particularly important in demanding technical-fabric applications, while Chinese manufacturers are increasing their presence in glass-fabric machinery. ^[13–16]
Supply-chain discussions currently indicate lead times of up to approximately two years for some sought-after Japanese electronic-glass weaving configurations, with occasional market commentary quoting two to three years for complete new-loom programmes.
That upper range should be treated cautiously. Toyota and Tsudakoma do not publish a universal two-year lead time, and actual delivery depends on specification, order quantity, factory loading and customer status. It is therefore best understood as current industry intelligence—not a manufacturer-confirmed standard lead time.
Even allowing for that qualification, the underlying constraint is credible. A project designed to produce hundreds of millions of metres of fabric annually requires a substantial loom population, plus warping, sizing, heat-cleaning, finishing, surface-treatment, inspection and material-handling equipment. When multiple producers expand simultaneously, they compete for the same specialist equipment-manufacturing and commissioning resources.

5. Loom installation is not the end of the ramp
Weaving is only one stage in the conversion of electronic yarn into laminate-ready fabric. After weaving, the material must pass through a tightly controlled finishing sequence:

1. Heat cleaning—removes organic sizing and other residues from the woven fabric.
2. Surface treatment—normally using silane chemistry, creates the required interface between the glass and laminate resin.
3. Inspection and grading—identify filamentation, broken ends, weave distortion, contamination and other defects.
4. CCL validation—confirms resin wetting, dimensional behaviour, electrical properties and laminate-processing consistency.
5. Customer qualification—may extend through PCB fabrication and, for critical applications, OEM approval.
For conventional 7628, the technical challenge is lower than for ultra-thin or low-CTE fabrics, but customers still require stable resin wetting, cleanliness, dimensional control and electrical performance. For 1080, 106 and other lightweight constructions, weaving productivity and usable yield are more difficult. For low-Dk/low-Df and low-CTE products, the learning curve is steeper again.
There are therefore three different dates hidden inside almost every capacity announcement:
• construction completion;
• mechanical commissioning and first production; and
• stable, qualified commercial output.
The third date is the one that matters to the CCL and PCB supply chain—and it may be many months later than the first.

6. Market outlook
The capacity is being built, but it will not arrive as one clean wave. It will be commissioned project by project, fabric style by fabric style and customer by customer.

The most likely outcome is not a uniform shortage across every glass style. It is a polarised market in which selected advanced products, ultra-thin fabrics and high-volume conventional constructions remain tight for different reasons and at different times.
For laminate manufacturers and PCB customers, this makes optionality, forward visibility and supplier relationships increasingly important. Qualification of alternative laminate systems cannot begin after the preferred glass construction has already become unavailable.

Conclusion
The electronic-glass-fabric market is responding, and the investment numbers are substantial. They should not, however, be mistaken for an immediate solution.
The shortage begins with electronic-grade glass yarn, but it does not end there. Loom availability, downstream processing equipment, technical know-how, production yield and customer qualification all limit the speed with which molten glass can become usable PCB reinforcement.
At the same time, the commercial incentive is directing much of the new capacity towards ultra-thin, low-Dk/low-Df and low-CTE products. That is entirely rational for fabric manufacturers, but it means conventional E-glass styles can remain constrained even while total industry capacity is increasing.
The market may therefore experience the apparent contradiction of record investment alongside continuing shortages, allocation and price inflation.
That is not evidence that the investment is failing. It is evidence of how long, specialised and capital-intensive the electronic-glass supply chain really is.
 
References and further reading
1. TrendForce, “Glass Fiber Cloth: The Underlying Material Shortage in AI Infrastructure,” 30 April 2026. Source
2. TrendForce, “Raw Material Inflation Deepens: FULLTECH Hikes Glass Fiber Cloth Prices Up to 30%,” 30 June 2026. Source
3. Shanghai Stock Exchange/Yicai Global, “China Jushi to Invest USD653 Million in Expanding PCB Raw Materials Output,” 15 May 2026. Source
4. China Composites Expo, “Jushi’s Zero-Carbon Smart Manufacturing Base in Huai’an,” 2026. Source
5. JEC Composites, “Jushi Puts Its Largest Electronic Glass Fibre Production Line into Operation,” 2026. Source
6. JEC Composites, “AI Boom: Kingboard Group Debuts 70,000-Tonne Electronic-Grade Glass Fibre Yarn Production Line,” 2026. Source
7. DIGITIMES, “Fulltech Plans THB3.1 Billion Thailand Plant to Support CCL Southward Shift,” 3 March 2026. Source
8. Thailand Board of Investment, investment approvals for advanced electronics and critical infrastructure, 8 July 2026. Source
9. Fulltech Fiber Glass Corporation, “Company Overview and Development History.” Source
10. Nitto Boseki Co., “Notice Regarding Expansion of Glass Cloth Production Capacity,” 29 August 2025. Source
11. Nitto Boseki Co., Integrated Report 2024. Source
12. Grace Fabric Technology, Draft Listing Document, Hong Kong Stock Exchange, 15 May 2026. Source
13. Toyota Industries Corporation, “Weaving Machinery.” Source
14. Toyota Industries Corporation, “Toyota Industries Releases the JAT910 Air-Jet Loom,” 28 November 2022. Source
15. Tsudakoma Corporation, “Technical Fabrics.” Source
16. Shandong Rifa Textile Machinery, “RFJA32 Fiberglass Air-Jet Loom.” Source
Research note: The loom lead-time discussion is deliberately presented as supply-chain intelligence rather than a manufacturer-confirmed universal specification. Delivery varies by configuration, order size, factory loading and commissioning scope.

Section 6
Members News 

New Gradings
Victor Lau - Fellow
Tom Hogan - Hon Fellow

We were pleased to re-establish contact with Tom Hogan, a long established member and it was very fitting that he was recently elected as an Honorary Fellow.

Tom was at the inauguration meeting of the ACT (Association of Circuit Technologists) at Caxton Hall in the early 1970’s, so he was probably one of the first members of the Association. He was elected Fellow in 1978 when Reuben Joseph was President.

He was a regular speaker at the ICT courses on PCB technology at Rewley Hall, Oxford. His specialty was flexible circuits which were just coming into use in the UK. He presented several papers at the Nepcon conferences at Brighton.

He had several articles about Flexible Circuits published in the UK and Europe. He worked at Forward Circuits, Tamworth when Pete Starkey was Technical Director. He is now retired (aged 89) and living in Dorset.

In the early days a Fellow was appropriately presented with an etched certificate acknowledging their standing in the Institute. Tom's was dated 1st August 1978! Congratulations Tom and thank you for your significant contribution to our industry.

Sales Director Transition at Amphenol Invotec

Amphenol Invotec has announced that Chris Haley has taken over as Sales Director, succeeding Terry Dowling, who is retiring after more than 42 years with Amphenol.

Chris has been with Amphenol Invotec since 2005 and brings extensive technical, operational and customer experience to his new role. Terry, whose long career has included helping to drive significant growth at Amphenol Invotec and developing many of the company's key customer relationships, is supporting Chris during the transition.

The two represented Amphenol Invotec together at the Farnborough International Airshow 2026, marking both Terry's contribution to the business and the beginning of the company's next chapter under Chris's sales leadership.

Electra Polymers Marks Retirement of Long-serving Finance Director

Electra Polymers has marked the retirement of Sue Large, who has stepped down after more than 30 years with the company.

During her long career as Finance Director, Sue played an important role in supporting the growth and development of the business and has been recognised by colleagues for her leadership, knowledge and commitment to the company.

Electra thanked Sue for her contribution over many years and wished her a long and happy retirement.

EuroTech Strengthens Quality Team

The EuroTech Group has strengthened its Quality department with three appointments as the company continues to invest in its people and manufacturing capabilities.

Dan Syder has been appointed Quality Manager, bringing experience in quality assurance and working with the company's aerospace customers. Kat Sharp becomes Quality Management Systems Manager and is working alongside the current QMS Manager in preparation for taking over the role following his retirement. Izzabella (Izzy) Jones, who originally joined EuroTech's laboratory as a technician, has progressed to the position of Quality Inspector and Administrator.

Quality Director Jeremy Wakeford said the strengthened team would support EuroTech's commitment to maintaining high quality standards as market requirements continue to evolve.

Alun Morgan Appointed CTO at Jiva Materials

Jiva Materials has appointed Alun Morgan as Chief Technology Officer. Alun brings extensive experience in PCB materials and technology to the company as it continues the development and commercialisation of its Soluboard® recyclable PCB substrate.

Jiva Materials are the developer of Soluboard®, the world's first fully recyclable rigid PCB substrate, with up to 67% lower carbon footprint compared to glass/epoxy technologies.

Section 7
Industry News

ADEON Continues Supporting MASS Via Filling Technology

ADEON Technologies has confirmed the continuation of its long-standing relationship with MASS following the acquisition of the German equipment manufacturer's business operations by SINGULUS Technologies AG.

Following discussions with SINGULUS management, ADEON has signed an agreement enabling it to continue selling and supporting MASS Via Filling Technology to the European printed circuit board industry. ADEON says the technical teams have also begun exchanging ideas on further developments and concepts.

SINGULUS, which is active in semiconductor and advanced manufacturing equipment, has expressed particular interest in MASS's vacuum and filling systems, while aiming to strengthen the company's position in the PCB industry through its collaboration with ADEON.

A-Gas adds Ultra-thick Photoresist from Micro Resist Technology

A-Gas Electronic Materials has expanded its advanced materials portfolio with the introduction of mr-P 22G, a positive-tone grayscale photoresist from Micro Resist Technology. Grayscale lithography enables controlled variations in exposure and development to create three-dimensional structures within a single resist layer, potentially reducing the number of processing stages required for complex structures.

The material supports ultra-thick films and deep, high-resolution patterning for applications including micro-optics, MEMS and MOEMS. Dr David Shaw, Business Manager at A-Gas Electronic Materials, said the company's focus is on helping customers understand how grayscale lithography can be applied effectively in practical manufacturing processes.

Amphenol Trackwise Manufactures 100-metre Multilayer Flexible Circuit

Amphenol Trackwise Designs has announced the successful manufacture of a 100-metre-long multilayer flexible printed circuit, extending the company's capabilities in long-length flexible PCB production.

Manufactured at the company's Stonehouse facility using its Improved Harness Technology (IHT), the circuit was produced using a continuous roll-to-roll process that enables flexible circuits to extend well beyond conventional PCB panel-size limitations. The achievement follows an earlier 72-metre circuit produced for the same industrial customer.

The technology is intended for applications where conventional wiring harnesses can be replaced by long flexible printed circuits, offering potential reductions in weight and space together with improved assembly repeatability.

MKS-Atotech Expands Manufacturing Capacity for Advanced PCB and AI Markets

Atotech has announced a major expansion of MKS' Atotech equipment manufacturing facility in Guangzhou, China. The US$25 million investment will add approximately 323,000 sq ft of manufacturing and operations space and is expected to double the site's production capacity by late 2027.

The expansion will increase capabilities in production, final assembly, logistics, testing and validation. MKS says the investment is being driven by sustained growth in AI-related markets, particularly semiconductor, advanced packaging and advanced PCB applications, where manufacturers require greater production scale and closer technical collaboration.

CCI Eurolam Continues Investment in European PCB Materials Capacity

CCI Eurolam is continuing to invest in its European production capabilities following the successful relocation of its German operations to a new 8,000 m² production and logistics facility in Düren.

The facility has substantially increased CCI Eurolam's capacity to serve the European PCB and electronics industry, and the company says further investment is now under way to increase its prepreg and laminate panelling capacity.

The expansion comes against a background of growing demand for advanced electronic materials driven by AI, high-end electronics and next-generation applications. CCI Eurolam says the investment is intended to strengthen European supply-chain capability while working closely with its global material partners.

Garner Osborne Joins Make UK Defence

Garner Osborne has joined Make UK Defence, the national trade association representing more than 850 companies in the UK defence manufacturing and supply chain. Garner Osborne links the move to its work in defence, aerospace and aviation.

GSPK Highlights Heavy Copper Capability for Power Electronics

GSPK Circuits is continuing to develop its UK manufacturing capability for high-power and high-reliability PCB applications, with particular emphasis on Heavy Copper and IMS technologies.

The company recently highlighted its capabilities at PCIM Europe 2026 alongside sister company TCL Elektronika, where discussions focused on PCB requirements for power electronics, thermal management and demanding high-current applications. GSPK's Heavy Copper capability includes constructions using very substantial copper thicknesses, with recent examples extending to 3 mm copper.

The company sees increasing opportunities for these technologies in power electronics, energy systems, defence and other applications where current-carrying capacity, thermal performance and long-term reliability are critical.

ICAPE Reports Strong Growth in PCB Demand

ICAPE Group has reported strong growth during the first half of 2026, with second-quarter revenue reaching €61.8 million, an increase of 22.9% compared with the same period last year.

First-half revenue reached €113.3 million, while the Group's order backlog stood at €82.1 million at the end of June, representing an increase of more than 70% year-on-year. ICAPE attributed the growth principally to higher sales volumes together with product price increases.

The Group continues to pursue both organic growth and expansion through acquisition in the international PCB market.

Jiva Materials Wins Hello Tomorrow Climate-tech Award

Jiva Materials has won the Climate Tech & Environmental Protection category at the 11th Hello Tomorrow Global Challenge, held in Amsterdam.

The Hampshire-based company was selected from more than 4,800 applicants worldwide and progressed through the competition as one of 100 finalists before taking the category award for its work on circular electronics and recyclable PCB materials.

Jiva's Soluboard® technology replaces conventional glass-fibre/epoxy PCB substrate materials with a naturally derived alternative designed to facilitate the recovery of copper and electronic components at end of life.

The award provides further international recognition for Jiva's approach to reducing electronic waste and improving the sustainability of PCB manufacture.

Merlin Flex Receives BAE Systems Partner 2 Win Award

Merlin Flex Ltd has received a Silver Tier Award from BAE Systems as part of its Partner 2 Win supplier programme.

The award recognises Merlin Flex's performance and contribution as a supplier to BAE Systems. Based in Hartlepool, Merlin Flex specialises in flexible and flex-rigid multilayer printed circuit boards and interconnection systems, supplying demanding markets including defence, aerospace and space.

The recognition reflects the company's continuing emphasis on quality and reliability in the manufacture of high-performance flexible circuitry.

Merlin Flex highlighted in Parliament

Merlin Flex was highlighted in the House of Commons during Defence questions in July as an example of the north-east's contribution to the UK defence industry. The discussion centred on increasing Ministry of Defence investment in British companies and the potential benefits for skilled employment and manufacturing in the region.

Polar Instruments Marks 50 Years of PCB Test Technology

Polar Instruments is celebrating 50 years since the company was founded by Doug Campbell in 1976. Its first product, the Toneohm 400A, was developed to help locate short circuits on PCB assemblies following wave soldering.

Over the following five decades Polar's technology has developed from PCB fault-location equipment into controlled-impedance testing, signal-integrity modelling and PCB stack-up design and documentation tools used by designers and fabricators worldwide.

Schmoll Maschinen Progresses New Global Headquarters

Schmoll Maschinen is progressing a major multi-million-euro investment in a new global headquarters and manufacturing campus at Rödermark, Germany.

Designed to accommodate around 500 employees, the new facility will consolidate the company's expanding operations into a single high-technology site supporting the development and manufacture of advanced PCB production equipment. The first machines are scheduled to come off the new production lines in autumn 2026.

The project reached another milestone in June when Schmoll employees gathered for the first company celebration inside the new headquarters while construction work continued.

Strip Tinning Secures £3m Funding to Scale Flexible Circuit Production

Strip Tinning has secured £3 million of funding to support the scale-up of UK manufacturing for cell-contact systems and flexible printed circuits used in electric-vehicle battery packs.

The award forms part of the UK Government's DRIVE35 Scale-up Fund, which is supporting technologies for zero-emission vehicle manufacture. Strip Tinning's project will increase manufacturing capability for cell-contact systems incorporating flexible printed-circuit technology, supporting the transition of these products into higher-volume automotive production.

Teledyne Labtech Accelerates RF and Microwave PCB Prototyping

Teledyne Labtech has introduced a Rapid Quote-to-Manufacture service aimed at reducing lead times for prototype and early-programme RF and microwave PCBs.

The service combines a matrix-based quotation system with streamlined programming and manufacturing workflows, enabling qualifying prototype PCBs to be shipped in as little as five days, subject to design complexity and material availability.

Based at Presteigne in Wales, Teledyne Labtech specialises in complex RF and microwave PCB manufacture for high-reliability applications including aerospace, defence, space and communications.

Ventec Sees AI Demand Reshaping PCB Materials Market

Ventec Europe is highlighting the increasing impact of AI infrastructure investment on the global PCB materials market. Ventec International has reported growing demand for high-speed copper-clad laminate materials as new generations of AI servers require increasingly demanding high-frequency and high-speed interconnect performance.

The changing market was also the subject of a recent EIPC technical presentation by Alun Morgan, Technology Ambassador at Ventec Europe, examining how the AI infrastructure build-out is disrupting the global PCB materials supply chain.

The developments come as Ventec continues to expand its global manufacturing footprint and capacity for specialist laminate and prepreg materials.

Section 9

ICT Council Members

Council Members

Steve Driver (Chair), Alun Morgan (Technical Director, Hon Sec, & Events), Chris Wall (Treasurer), Leigh Allinson (Vice-Chair), Richard Wood-Roe (Journal Editor & Web Site), Brian Morgan (Membership Secretary), Mat Beadel, Neil Chamberlain, Emma Hudson, Pete Starkey, Francesca Stern. 

Section 10

Editor's Notes

The ICT Journal

Richard Wood-Roe
Journal Editor

Instructions / Hints for Contributors

We really look forward to any input you have. Technical papers, company news, personal news, industry comments or observations.

As it is a digital format the length is not an issue. Short is better than none at all!

I really do look forward to receiving articles for publication.

Richard Wood-Roe

This email address is being protected from spambots. You need JavaScript enabled to view it.