The Journal of
The  Institute of Circuit Technology
Vol 17 No 3
July 2024

Links to Contents 

10

Richard
Wood-Roe
Journal Editor

In this issue of The Journal our first paper is from Shenzhen University and outlines the research into the mechanism of chip removal during back drilling of high speed pcb's. 

Our second paper is from Kaunas University of Technology, Lithuania and reviews non-destructing test methods for pcb's.

Finally we have a technical paper from Atotech identifying soldering defects on immersion tin and the impact of the tin-oxide layer

It is sad to report the passing of Roy Polson, one of our industry founding fathers.

I have found a generous amount of items to add to the membership and industry news sections including an initiative from HMGC. In its latest challenge, HMGCC Co-Creation wants companies and academia to apply to a five-month, funded project, aimed at developing ways to robustly assure printed circuit boards (PCBs).

Our future events include our 50th Anniversary Dinner and Symposium. The Christmas Seminar takes place in December at Meriden.

I hope you find the contents of the Journal interesting. This is a long document so please remember the embedded links that allow you to jump back to the contents page. This email address is being protected from spambots. You need JavaScript enabled to view it.

Emma Hudson
Technical Director and Membership Secretary

           2024

            Details 

We have the pleasure in announcing our 50th Anniversary Annual Symposium followed by a celebratory dinner at the Puckrup Hall Hotel & Golf Club, Tewkesbury, on the 8th of October and we’d love members to join us.

We’ll be sending more details out over the coming weeks about the day and what will be included.

Chip Removal Mechanism and Hole Cleanliness in Back-drilling of High-speed Printed Circuit Boards

Zhuangpei Chen, Hongyan Shi, Tao Zhu, Xianwen Liu, Zhaoguo Wang, Qian Zhou

State Key Laboratory of Radio Frequency Heterogeneous Integration, Shenzhen University, Shenzhen 518060, People’s Republic of China

Abstract: Micro-holes are channels for signal connection between layers of printed circuit boards (PCBs), and excess invalid hole copper in through holes can destroy the integrity of signal, which is usually removed by back-drilling. However, as high-speed PCBs evolve towards miniaturization and high density, it is difficult to remove chips during back-drilling and easily cause micro-holes plugging with drilling debris, seriously affecting the performance of high-speed PCBs and even leading to scrap.

Therefore, the chip removal mechanism of high-speed PCB back-drilling is studied to solve hole plugging in this paper.

Firstly, kinematic methods are used to analyze the mechanical behavior and motion law of chip formation, and then the expressions of chip removal force and chip moving speed are proposed.

Secondly, the chip removal model of back-drilling is established, an evaluation index of chip removal capability is put forward, and the influence rule of machining parameters on chip removal of back-drilling is analyzed afterwards.

Finally, back-drilling experiments of high-speed PCB are carried out to observe the chips winding around the drill bit and calculate the hole plugging rate of back-drilling. The experimental result demonstrates that the number and density of winding chips in the drill bit slightly decrease with the increase of feed rate, and the hole plugging rate rises almost proportionally. Increasing the spindle speed can greatly improve the chip winding of tools and hole plugging, and effectively reduce the chip removal force of back-drilling. The research presented provides theoretical guidance for solving the bottleneck problem of micro-holes plugging during back-drilling in the high-speed PCB industry.

1. Introduction

The commercialization of 5th Generation Mobile Communication Technology (5G) has greatly promoted the technological progress of electronic information industry, and communication technology is evolving towards large capacity, low latency, and high-speed transmission. It also puts forward higher requirements for current 56 Gbps and future 112 Gbps signals transmission performance of high-speed printed circuit board (high-speed PCB). Micro-holes in PCB are the channels for the signal connection between layers, while the excess invalid hole copper in through hole would cause signal delay, reflection and resonance, which destroy the integrity of high-speed signal. In order to achieve higher speed signal transmission, high- speed PCBs are usually back-drilled [1][2]. Back-drilling is a secondary drilling method, in which copper plated through-holes are drilled from the back to remove excess copper (Fig.1), thereby improving high-speed signal transmission characteristics. However, the thickness of high-speed PCB is getting larger, the structure is becoming more complex, and the through-hole is getting smaller. It leads to the difficulty of chip removal in back-drilling, which could easily cause micro-hole plugging and seriously hinder the higher-speed development of signal transmission [3]. Back-drilling hole plugging has become a knotty issue in the PCB industry. Therefore, it is essential to study the chip removal mechanism of high-speed PCB back-drilling, and attempt to find the key breakthrough to solve the hole plugging problem of back-drilling.

Fig. 1 Signal connection and back-drilling

In view of the micro-hole plugging problem during high-speed PCB back-drilling, it is necessary to make clear the causes. Scholars typically explore the material properties of PCB and the characteristics of back-drilling technology. The essence of hole plugging is that the drilling chips cannot be normally removed, i.e., the generation capacity of drilling chips is greater than that of chip removal. When back-drilling, the copper foil is mixed with resin and other materials in the chip, and the through-hole plated copper is hard to cut off due to its excellent ductility. Moreover, the chip removal space of planted through-hole is further reduced, so it is difficult for drilling chips to evacuate under these combined effects.

In this paper, the chip removal model of high-speed PCB back-drilling was established based on the analysis of mechanical behavior and motion speed in the process of chip formation, and then an evaluation index for chip removal capability was put forward. Through the high-speed PCB back-drilling experiment, the micro-hole plugging phenomenon was studied from chip winding of tools, hole plugging rate and chip removal force, so as to clarify the influence mechanism of processing conditions on chip removal in back-drilling. Finally, the key factors of hole plugging during high-speed PCB back-drilling were clarified, and specific solutions were given. The present research helps to solve the processing problem of hole plugging in high-speed PCB back-drilling, and is of great significance for promoting the key technology of back-drilling, ensuring high-speed signal transmission, and reducing product loss as well.

2. Chip removal model of high-speed PCB back-drilling

2.1 Mechanical analysis of chip removal process
After leaving the rake face of the drill, the workpiece material forms chips with a certain shape and moves along the drill flute. The chip removal efficiency of high-speed PCB back- drilling depends in part on the force of the chips while moving. In this study, the mechanical behavior of the maximum size chips that could be generated during back-drilling was analyzed. The following assumptions are necessary for the motion analysis of the unit chip moving:

(1) The size of the unit chip is smaller than the cross-sectional area of the drill flute of the drill bit. Thus, the influence of the unit chip size on the chip removal process is ignored.
(2) The unit chip removal process is smooth and not compacted. The interaction force between the unit chips is very small compared to the friction force and can be ignored.

The force acting on the unit chip in the drill flute of the drill bit is shown in Fig. 2. When the drill bit rotates at high speed during operation, the centrifugal force generated squeezes the chips onto the hole wall and creates friction with the hole wall. This force provides upward force along the direction of the drill flute to promote chip evacuation. On the other hand, when the chip moves upward, its movement is hindered by the friction of drill flute and gravity, which makes it difficult to remove the chip.

Fig. 2 Force model of unit chip

 2.2 Chip extruding speed
During the back drilling-process, the workpiece material changes from solid form to chip form, and the density of the chip material decreases with increasing volume. The material volume removed by the back-drilling per unit time, V_c,removal , can be: 

V_c,removal = A_hole x V_feed

where A_hole  is the cross-sectional area of material drilling and V_feed is the feed speed of bit.

Furthermore, the expansion coefficient of the removed material also changes after shape transformation. Assuming that the flow rate of the deformed chip is V_{c, form} , then the expansion ratio K_v is:

K_v = V_{c, form} / V_{c, removal}

When the chip enters the spiral groove at initial speed, at least a length is required to accommodate the newly generated chips. The chip speed must exceed a certain critical speed per unit time to avoid chip compaction.

The minimum speed at which the chip can move smoothly in the drill groove without compaction is named as the chip extrusion speed. In deep hole drilling, new chips will be generated continuously with the feed of drill bit. If the actual chip moving speed is slower than the chip extrusion speed the chips will squeeze each other, resulting in increased friction between chips and the flute surface. It would further reduce the chip moving speed, leading to chip plugging and unstable back-drilling process.

2.3 Chip moving speed
Chips entering the drill flute achieve a high moving speed under the feed and rotation of the drill bit. The overall chip moving speed generated by rotation is closely related to the spindle speed, and the helix angle of the drill bit.

Fig. 3 Movement and pitch of spiral chip

After the workpiece material is cut off, it enters the drill flute, and spiral curling occurs under the action of flute space and tool feed. The initial moving speed depends on both spindle rotation and the axial feed. The overall and the relative chip moving speed can be calculated.

2.4 Analysis of chip removal process
Generally speaking, it can be considered that hole plugging can begin in the first unit of chip formation. The chip has a certain speed as it leaves the workpiece material, and followed by the chip leaving the cutting edge it quickly reaches an initial steady state after entering the drill flute. Under the movement of the drill tool, chips move upward along the drill flute, at this time the chip removal force will gradually slow down the moving speed. Once chip moving speed lags behind chip extrusion speed the chips will squeeze each other and even plug in the micro-hole.

For the chip removal process of high-speed PCB back-drilling, the final moving speed of chip will decrease to zero under the chip removal force obstruction, and the distance that the chip can move during chip removal process directly determines the probability of hole plugging.

Therefore, the concept of chip removal distance is proposed to measure the capability of chip removal. In the process of chip removal, the moving speed of chip will always affect chip removal force, and conversely, the acceleration generated by force will also change the moving speed.

As the feed rate increases, the chip removal distance first rises and then drops under the conventional back drilling parameters. Nevertheless, the changes in force and distance are extremely small in value, which means that it is unlikely to improve the chip removal process by adjusting the feed rate.

Fig. 4 Effect of feed speed on chip removal process

The effect of spindle speed on the chip removal process is shown in Fig. 6. It is noted that the value of chip removal force increases with the spindle speed and the change is particularly evident at high spindle speed. As the spindle speed grows, the chip removal distance first increases rapidly, reaches the maximum at a certain high spindle speed, and then decreases slowly.

Fig. 5 Effect of spindle speed on chip removal process

It can be seen from the analysis of chip removal force and chip removal distance that the influence of feed speed on the chip removal process of high-speed PCB back-drilling is much less than that of spindle speed. Ideally, the chip removal process could be greatly optimized by increasing the spindle speed within a certain range, as long as the spindle speed at the optimum chip removal distance is determined. In conclusion, adjusting the spindle speed would be one of the best ways to reduce the hole plugging phenomenon in back-drilling.

3. Back-drilling experiment of high-speed PCB
In order to verify the chip removal model and reveal the influence of drilling parameters on chip removal force and chip removal distance, high-speed PCB back-drilling experiments were set up. The chip removal process of back-drilling was analyzed from the aspects of chip removal force, chip winding and hole plugging rate. In addition, the experiments with different tool structures were supplemented for further study of back-drilling hole plugging.

3.1 Experimental materials and apparatus
The workpieces were basic board S1150G made by Guangdong Shengyi Technology Co., Ltd., with a total thickness of 1.6 mm and 6 signal layers (copper thickness 35 μm). In order to carry out back-drilling experiments, through-holes drilling and copper plating were finished. The main treatment process flow of back-drilling boards was shown in Fig. 6. Through holes with diameter of 0.3 mm were drilled on the basic board, followed by copper plating on the through holes surface and circuit board surface with a thickness of 35 μm, as shown in Fig. 6(a). The finished high-speed PCB for back-drilling and through-hole copper plating as shown in Figs. 6(b) and 6(c).
The tools were A129BD back-drill special bit produced by Shenzhen Jinzhou Precision Technology Co., Ltd., and the basic structural parameters were detailed in Table 1. According to the recommended table of micro-drilling parameters given by manufacturer, the optimum spindle speed was 85 krpm, the feed rate was 28 μm/rev and the feed speed was 40 mm/s.

Fig.6 Processing flow and finished product of high-speed PCB for back-drilling

Table 1 Basic structural parameters of A129BD

High-speed drilling machine CK-01D produced by Shenzhen Zhijian Automation Equipment Co., Ltd. was used for back-drilling. The maximum speed could reach 200 krpm, the positioning accuracy was ±0.005 mm, and the repetition accuracy was ±0.0025 mm. The high-precision microforce measuring system (including 9256CQ01 dynamometer) provided by Kistler could obtain six-axis force signals, and it was used to measure the thrust force during high-speed PCB back-drilling. The back-drilling experimental platform was shown in Fig. 7(a). The ultra-depth electron microscope Keyence VXH-7000 could freely change the magnification in the range of 20 to 6000 times with ultra-high resolution of 4K, as shown in Fig. 7(b), for observing chip morphology, micro-hole plugging, etc.

To count plugging holes, a micro-hole inspection visual system was built, which consisted of industrial camera Hikrobot MV-CS200-10GM, optical lens MVL-KF2528M-12MP and LED light source, etc., as shown in Fig. 7(c). With the features of low noise, high resolution and excellent graphics, the system would quickly check high-speed PCB and get the number of plugging holes.

Fig.7 Back-drilling experimental platform

3.2 experimental scheme
The chip removal process of high-speed PCB back-drilling is greatly affected by the processing parameters (spindle speed, feed speed, feed rate) and tool structure parameters (helix angle, point angle). Therefore, spindle speed of 60, 85, 110 krpm and feed speed 25, 40, 60 mm/s were selected within the range of conventional machining parameters for high-speed PCB back-drilling, and three micro-drills with different structures were used for comparison.

The experiment of back-drilling hole plugging research was set up, as shown in Table 2. Chip winding of the drill bit is mainly affected by feed rate. Back-drilling at a low spindle speed (e.g. 40krpm) is also prone to obtain micro-drills with winding around chips. Hence the back-drilling chip winding experiment shown in Table 3 was conducted.

Table 2 Experimental scheme of back-drilling hole plugging

Table 3 Experimental scheme of back-drilling chip winding

The analysis method of back-drilling experimental results was by means of ultra-depth electron microscope, micro-hole inspection visual system and microforce measuring system. Drill bits that had back-drilled 100 holes were used as samples to observe the cutting tool winding condition. High-speed PCBs that had 1000 back-drilled  holes were used as samples to count the number of plugging holes and then calculate the plugging rate. The drilling force signals during high-speed PCB back-drilling were collected and filtered to analyze the chip removal force.

4. Results and discussion

4.1 Chip tangling
As the drilling depth increases, chips do not maintain their spiral shapes. At this time, the chip moving speed of inner drill bit increases, resulting in a decrease in chip thickness, while the decline in chip moving speed at the outer drill bit increases the thickness. Due to the small strength of the thin chip material, chips are sheared into zigzag shape and string chips are produced under the movement of the drill bit. With the change of chip moving speed, the stress changes on the inner and outer sides of the chips. The resulting bending moment makes the chips gather and lead to chips winding around drill bit. Further, problems such as abnormal back-drilling depth and micro-hole plugging occur.

It can be seen from Fig. 9 that the chip winding is more serious when back-drilling at low feed rate. With the increase of feed rate, the number and density of chips winding around the bit decrease gradually, and the chip winding situation improves. 

Fig. 8 chip winding of tool at different feed rates (n=40krpm)

The influence of spindle speed on chip winding is more obvious, as shown in Fig. 9, with the increase of spindle speed, the amount of chip winding is significantly reduced. As the spindle speed progresses, the chip moving speed greatly raises, thereby increasing the chip removal distance of copper chips and preventing the chips from gathering and squeezing each other. The experimental results show that larger feed rate or higher spindle speed can improve the chip winding phenomenon, especially increasing spindle speed, which would be the most effective method to tackle the chip winding problem in high-speed PCB back-drilling.

Fig. 9 chip winding of tool at different spindle speeds (f=50μm/r)

4.2 Hole plugging
Owing to the small diameter of back-drilling hole, the chip removal space of micro-drill spiral groove is pretty limited. Plated copper in micro-holes has a relatively large thickness and excellent ductility, and it is easy to cause hole plugging when the chips are squeezed together. Several common cases of back-drilling hole plugging are shown in Fig. 10. As shown in Figs. 10(a)-(c), there are complete spiral copper foil chip, spiral prepreg (composed of resins, epoxy fiberglass cloth, etc.) chip and short ribbon prepreg chip in the micro-hole. These types of chips have been completely removed from the workpiece, but remain in the micro-holes due the poor chip evacuation ability, which can be solved by using common vacuum cleaner. Holes plugging in Figs. 10 (d)-(f) are more serious, with copper foils that have not been completely cut off, and the chips still connected to the hole wall. This issue is mainly due to the high ductility of copper, and the poor cutting quality of drill bit cutting edges, resulting in incomplete material cutting and unable to form independent chips.

Fig. 10 Chip observation of plugged holes

Experimental research was conducted on the plugging problem of micro-hole back-drilling in terms of processing parameters and tool structure. The results are shown in Table 4. In general, the hole plugging rate of back drilling is low, with the highest reaching 18.6%. The influence of processing parameters on hole plugging rate is shown in Fig. 12. It shows that the hole plugging rate is positively correlated with the feed rate and negatively correlated with the spindle speed, in which spindle speed has a greater influence. With the increasing of spindle speed, the hole plugging rate in back-drilling decreases significantly. The main reason is that the volume of material removed per unit time increases with the feed speed, and chips are not evacuated smoothly, resulting in a higher hole plugging rate. As for the spindle speed, undoubtedly, increasing it can reduce the material generated, and also increase the chip moving speed. Chip removal process is enormously smooth under the combined action, thus the spindle speed is the key factor to reduce the hole plugging rate.

Table 4 Results in back-drilling experiment

Fig. 11 Effect of processing parameters on hole plugging rate

Since the amount of material cut off is closely related to hole plugging rate, the effect of the feed rate on plugging rate is analyzed, as shown in Fig. 13. The result reveals that the hole plugging rate generally increases with the feed rate, but it is greatly affected by the spindle speed. By observing the relationship between feed rate and plugging rate at different spindle speeds, it can be seen that the plugging rate is almost proportional to the feed rate. However, this relationship could be broken out by increasing the spindle speed, as illustrated by the significant decline plugging rate at high speeds of 85krpm, 110krpm. The results are consistent with the chip winding experiment, indicating that lower spindle speed tends to cause chip winding, and also hinders chip removal.

Moreover, the structure of the tool also affects the chip removal to a certain extent. For comparison, a drill bit with larger helix angle (35°) and a drill bit with smaller point angle (130°) was performed in back-drilling experiment. As a result, the hole plugging rate was higher. The reason is that the larger spiral angle increases the extrusion speed of chips, while the smaller drill point angle is not conducive to the generation of spiral chips, and both are prone to hole plugging and increasing chip removal force.
Fig. 12 Effect of feed rate on hole plugging rate

The thrust force of high-speed PCB back-drilling under different processing parameters is obtained by signal filtering and average force calculation. As shown in Table 4, the thrust force of back-drilling is relatively small, ranging from 0.18 N to 0.23 N. Based on the micro-hole drilling force formula, the power function trendline is selected to fit the back-drilling force. As shown in Fig. 14, the thrust force increases with the feed rate on the whole, with a small deviation from the trendline. It is found that the thrust forces at spindle speed 110 krpm are all below the trendline, whereas those above the trendline are all at 60 krpm and 85 krpm, indicating that back-drilling at high speed can effectively reduce the chip removal force. The increment of spindle speed enlarges the chip friction, nevertheless, it greatly increases the chip moving speed, so that the chip removal distance is larger. With the decrease of chip winding problem, the whole back-drilling process becomes smoother.
Fig. 13 Effect of feed rate on thrust force

From the analysis of chip winding, hole plugging rate and chip removal force, the following conclusions could be drawn: Increasing the feed rate can slightly reduce the occurrence of chip winding but raise the hole plugging rate in high-speed PCB back-drilling. Spindle speed has the most obvious effect on back-drilling hole plugging, its growth significantly reduces chip winding and plugging rate, as well as effectively reduces chip removal force. As for the tool structure, smaller helix angle and larger drill point angle also facilitate chip removal. Therefore, increasing the spindle speed would be the optimal choice to solve hole plugging problem in back-drilling. This measure could greatly reduce the hole plugging phenomenon and also reduce the chip removal force, thereby improving the tool life. Besides, it is also a useful method to enlarge the chip removal space or chip removal efficiency by upgrading the tool structure, so as to reduce the occurrence of hole plugging.

5. Conclusions
Aiming at the hole plugging challenge of high-speed PCB during micro-hole back-drilling, the paper conducted in-depth research on the chip removal mechanism. The chip removal model of back-drilling was established and an evaluation index of chip removal capability was proposed. Also, the chip winding, hole plugging rate and chip removal force were investigated by back-drilling experiment. The influence mechanism of processing parameters and tool structure on back-drilling hole plugging was clarified, and the specific scheme to improve the 
hole plugging phenomenon was put forward. The conclusions of this paper can be summarized as follows:
(1) Based on the mechanical behavior and motion rule of chips, a chip removal model for high-speed PCB in back-drilling including removal force, moving speed and removal distance is established. Thus, the influence mechanism of processing conditions on the chip removal capability was revealed.
(2) From the model, the chip extruding speed increases with the feed speed, which is not conducive to chip evacuation, but can effectively reduce the tool chip winding. While the spindle speed has a significantly effect on the chip moving speed, its growth can enlarge the chip removal distance to avoid hole plugging. This is also confirmed by the back-drilling experiment.
(3) Both the theoretical analysis and the experimental results indicate that increasing the spindle speed would be the most effective method to solve the hole plugging in back- drilling. In addition, smaller helix angle and larger point angle of the drill bit reward less hole plugging.

Acknowledgments
This research is supported by the National Natural Science Foundation of China (No. 52075344), the National Key Research and Development Program of China (No. 2020YFB1708500), and the Science and Technology Innovation Commission Shenzhen (Nos. JSGG2019152602381 and JSGG20200914113603008).

Declaration of competing interests
The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.

Comparison of Non Destructive Testing Techniques for PCB's Produced Using Traditional vs Additive Processes.

Elena Jasiūniene^1,2,*, Renaldas Raišutis^2,3 , Vykintas Samaitis² and Audrius Jankauskas²

¹ Department of Electronics Engineering, Kaunas University of Technology, Lithuania;
² Prof. K. Barsauskas Ultrasound Research Institute, Kaunas University of Technology, Lithuania; 
³ Department of Electrical Power Systems, Kaunas University of Technology, Lithuania
* Correspondence: This email address is being protected from spambots. You need JavaScript enabled to view it.

Dr Elena Jasiūnienė
Chief Researcher at Ultrasound Institute, Kaunas University of Technology 

Abstract: Multilayer printed circuit boards (PCBs) can be produced not only in the traditional way but also additively. Both traditional and additive manufacturing can lead to invisible defects in the internal structure of the electronic component, eventually leading to the spontaneous failure of the device. No matter what kind of technology is used for the production of PCBs, when they are used in important structures, quality control is important to ensure the reliability of the component. The nondestructive testing (NDT) of the structure of manufactured electronic components can help ensure the quality of devices. Investigations of possible changes in the structure of the product can help identify the causes of defects. Different types of manufacturing technologies can lead to diverse types of possible defects. Therefore, employing several nondestructive inspection techniques could be preferable for the inspection of electronic components. In this article, we present a comparison of various NDT techniques for the evaluation of the quality of PCBs produced using traditional and additive manufacturing technologies. The methodology for investigating the internal structure of PCBs is based on several of the most reliable and widely used technologies, namely, acoustic microscopy, active thermography, and radiography. All of the technologies investigated have their advantages and disadvantages, so if high-reliability products are to be produced, it would be advantageous to carry out tests using multiple technologies in order to detect the various types of defects and determine their parameters.

1. Introduction
Multilayer printed circuit boards (PCBs) are an important part of multiple devices¹. Today, PCBs can be produced not only in the traditional ways, such as layering, photolithography, drilling, and plating, but with recent advances in 3D printing technologies, they can also be produced additively^2-4. Additive manufacturing has the potential to transform electronic component fabrication into a more flexible and customizable manufacturing process, surpassing the limitations of planar designs^5-8. Other benefits of the additive manufacturing of electronic components include the efficient use of material resources, waste reduction, and the ability to produce specialized and personalized products on demand⁹. Potential applications could include the ability to 3D print electronics during space missions¹⁰. One example of inkjet additive manufacturing technology is the DragonFly LDM electronic sub-assembly technology, which enables the serial production of state-of-the-art electronic PCBs in laboratory conditions by using simultaneous deposition for conductive and dielectric ink^3,5,6. The additional benefit of designing and manufac- turing electronic devices using in-house resources is that, in this way, the risks associated with designing and manufacturing products in external, third-party environments are avoided: this protects against the possible leakage of product technological information, the copying of devices, or the introduction of hidden defects during manufacturing.

The DragonFly LDM equipment uses a newly developed, multi-material deposition technology that has a number of advantages, such as fast device design, safe production, easy product modification, etc.¹¹. Nevertheless, there are no specific data on possible structural changes or the degradation of products using the DragonFly LDM manufacturing technology, both during manufacturing and in service. PCBs are produced using multiple composite materials that create the electronic components of the product through the simultaneous deposition of traces using a silver nanoparticle suspension and substrates by using acrylate inks.

PCBs that are part of electronic components in, i.e., military devices, should be reliable and cannot fail unexpectedly¹. No matter what kind of technology is used for the production of a PCB, when they are used in important structures, their quality has to be ensured.

Traditional and additive manufacturing can cause invisible defects in the internal structure of the electronic component¹, ultimately leading to the spontaneous failure of the device. Quality control for the PCBs is important in order to improve the reliability of these components. Defect detection before the assembly of electronic components can reduce repair costs and help prevent unexpected failures in the future. This is of primary importance when additive processes are used for manufacturing PCBs. Therefore, the nondestructive evaluation of the structure of manufactured electronic components can help ensure the quality of these devices. Investigations into changes in the product’s structure could help identify the causes of defects and modify the additive manufacturing process accordingly until the desired quality has been achieved. However, different types of manufacturing technologies can lead to various types of possible defects; therefore, distinct nondestructive inspection techniques for the inspection of electronic components may be required. PCB quality control is challenging because of the variety of types of defects that can form in components because of mishandling, technical faults in the production process, environmental influence, or human error¹.

There are several NDT techniques that are used for the inspection of PCBs manufactured using traditional technologies. Moreover, it is also known that there is no technique available that would allow for the detection of all types of defects in PCBs¹². Different techniques are suitable for detecting specific types of defects, each with its own advantages and limitations¹².

Previously, the most popular NDT technique for PCB inspections was manual visual inspection, which is now replaced by automated optical inspection (AOI)^1,13,14. This technique is based on visual inspection and is good for surface defect detection. Lately, many different image-processing methods have been introduced to make these techniques more efficient ¹. For example, Melnyk et al. implemented thinning and flood-fill algorithms for short and open defect detections in PCBs¹⁵. In addition, machine learning algorithms and deep learning-based methods such as convolutional neural networks (CNNs) have also been integrated into AOI systems to improve inspection speed and defect detection accuracy¹. Some studies have presented AI-based inspection to detect corrosion on electronic components¹⁶. Moreover, in multilayer PCBs, defects can also form at the interfaces between the layers, not only on the surface; so, using AOI, they would remain undetected.

For PCBs manufactured using traditional technologies, radiography is the established inspection technique. Radiographic testing is good for the detection of soldering defects (open or short solder joints, voids in the solder, missing/misplaced components, etc.)^12,17. Scott et al. presented technology to enhance radiographic inspection by providing material type and thickness information by coupling the analysis of the images with machine learning algorithms¹⁸. To automatize the evaluation of radiographic images, deep-learning-based methods have been introduced for the detection of solder joint defects¹⁹. However, digital radiography provides PCB X-ray images with overlapped information²⁰: it is challenging to pinpoint from radiographic images in which layer a defect is located. When reconstruction of the images of separate layers of PCBs is required, X-ray-computed tomography is the better option¹⁷. Nonetheless, image artifacts due to beam hardening and streak artifacts due to metallic components can obscure the images obtained²¹.

Acoustic microscopy is especially suitable for the detection of delamination between conductive layers and the substrate^12,22. Raisutis et al. developed a novel signal processing method based on the adaptive numerical model to improve the reliability of ultrasound inspection²². Wang et al. used laser-induced ultrasound for the detection of delamination-type defects in PCBs²³. Thermal imaging, specifically, infrared thermography (IRT), has been increasingly used for defect detection in various components, including PCBs²⁴. Avdelidis et al. used pulsed thermography for defect detection in PCBs²⁵, while Wiecek et al. used thermography for the estimation of solder thickness in PCBs²⁶. A pulsed thermography based inspection technique using the digital twin methodology was proposed by Liu et al. for the inspection of electronic components²⁷.

In addition to the use of single techniques for quality control of PCBs, there have been several attempts to use multiple techniques as well. I.e., Li et al. used a multi-sensor image fusion of polarization information and infrared imaging to improve defect detection accuracy¹³. Nicholson et al. developed a comprehensive online quality control system for PCBs that includes AOI, thermography, digital radiography, and acoustic microscopy¹². All of these technologies allow us to look inside multi-layered components without disassembling or damaging them and to identify damage to internal structures or deviations from requirements. The inspection of the quality of a PCB before assembly is crucial to understanding whether additive manufacturing technology, in some cases, can be expected to replace traditional PCB manufacturing and provide the same quality of PCBs. Nevertheless, given the relatively small dimensions of electronic components and the extremely small potential damage, this task is not trivial.

In this study, we investigated the potential of multiple NDT techniques, namely, thermography, acoustic microscopy, and radiography, for the inspection of PCBs manufactured using two distinct technologies—traditional and additive manufacturing. For this purpose, a specialized PCB was designed and manufactured using traditional and additive manufacturing technologies. A comparative analysis of different NDT techniques for evaluating the quality of PCBs produced using traditional and additive manufacturing technologies is presented. In addition, defects were intentionally introduced into another additive-manufactured PCB, and a comparison of the ability of different NDT techniques to detect various types of defects is presented. In the following sections, the samples used in this study and the artificial defects are described. Next, the principles of NDT techniques used for the inspection of PCB boards are introduced, followed by a detailed comparison of the inspection results between traditional and additive manufacturing technologies and the defect detection capabilities of additive manufacturing boards.

2. Materials and Methods
In order to compare and evaluate the potential of different NDT techniques, a specialized PCB was designed using Altium Designer (San Diego, CA, USA) software package and later produced using traditional and additive manufacturing technology. In addition, in one more additively produced PCB, defects were intentionally introduced. The PCBs produced using different technologies were investigated using the following techniques: thermography, acoustic microscopy, and radiography.

2.1. Samples
For a comparison of PCBs manufactured by traditional and additive manufacturing technologies, two sets of boards were prepared. The PCBs were 56 × 65 mm in size and composed of 4 layers with dedicated internal ground and power planes. A layer stack for PCB production using traditional manufacturing technology (layering, photolithography, drilling, and plating) is presented in Figure 1.

Figure 1. PCB layer stack for the manufacturing of boards using traditional technology.

Keeping the same stack-up as in the case of manufacturing using the traditional method, the additive manufacturing of PCBs was performed using the DragonFly LDM. The main difference between the manufacturing technologies used was that, for the use of the DragonFly LDM, the base is UV-curable acrylate (Dielectric Ink 1092 NanoDimenion, Waltham, MA, USA). Meanwhile, as a conductive material in PCB production, an AgCite 90072 Silver Nanoparticle Conductive Ink (NanoDimension, Waltham, MA, USA) was used. In Figure 2, photos of PCB boards produced using traditional (a) and additive (b) tech- nologies are presented. In addition to PCBs without defects, artificial defects were introduced into another additively manufactured board. In this case, we chose not to create artificial delamination-type defects, which would imitate disbonding between the conductive layer and substrate. This decision was made due to difficulties in controlling the defect size and position and to ensure the reproducibility of such defects. Therefore, the defects considered were missing vias, tracks, and SMD pads, as well as an incorrect pitch between pads and tracks with width reduction. The positions of the defects are shown in Figure 3, while their description is provided in Table 1.

(a)                                                           (b)
Figure 2. Photos of the PCB boards produced (a) using traditional technology and (b) with additive manufacturing technology.

(a)                                                      (b)
Figure 3. Layout of additively manufactured PCBs (a) with defects and (b) without defects. Explanation of the numbered zones are given in Table 1.

Table 1. Artificial defects created in additively manufactured PCBs.

.

2.2. Thermography
Infrared thermography (IRT) is a non-contact NDT technique that remotely measures temperature variations over the surface of an object of interest, generating a thermal image. This technique relies on detecting the infrared radiation emitted by an object, a process influenced by the object’s temperature, emissivity, surface conditions, and environmental factors¹³. Faults or defects in PCBs can lead to abnormal temperature increases and variations in temperature distribution, which can indicate the presence of potential defects and their respective positions. Two common variants of IRT are available, namely, passive and active thermography, depending on whether an external energy source is used to induce a change in the object’s temperature.

In this study, an active IRT technique was used. The printed circuit board (PCB) samples (Figure 2) were examined with a FLIR 1020C thermal imaging camera at high resolution. The number of pixels was 1024 × 768. Thermal sensitivity was <20 mL at +30 ◦C. The wavelengths of the detected thermal radiation were from 7.5 µm up to 14 µm. The distance between the surface of the test object and the lens of the thermal imaging camera was set to 700 mm. A thermal camera was attached to the photostat to obtain high-quality thermal images and to avoid the effects of blurriness. The sample was placed on a polystyrene foam substrate (12 mm thick), and the substrate was placed on the ceramic surface of a Witeg MSH-20D hotplate (temperature 40 ◦C). Figure 4 shows a schematic of the experimental setup implementing the active thermography method.

Figure 4. Schematic diagram of the application of a FLIR 1020C high-resolution thermal imaging camera and a Witeg MSH-20D hotplate for printed circuit board (PCB) testing.

2.3. Acoustic Microscopy
Scanning acoustic microscopy (SAM) employs high-frequency ultrasonic waves to examine the internal structure of various components. It allows for the detection and identification of internal delamination, voids, material property changes, and other defects within materials and structures. The working principle of this technique is based on the pulse–echo method (as shown in Figure 5). The probe emits ultrasound waves that penetrate the material. When there are material interfaces, defects, or variations in material density or elasticity, a part of the wave is reflected back to the transducer. Consequently, SAM can create ultrasonic images that display the distribution of reflection magnitudes across the scanning area. The defects will act as unexpected reflectors, whereas changes in material properties will result in varying signal attenuation. SAM is highly sensitive to the presence of delamination, which is difficult to detect using X-ray radiography. It is a recognized technology for nondestructive quality control, inspection, and failure analysis in microelectronic components and materials and is routinely used for the inspection of integrated circuits and other components.

The experimental setup of the system used for the SAM of manufactured PCB boards is presented in Figure 5. For all samples, measurements were conducted in pulse–echo mode on one side of the sample. To ensure acoustic coupling between the sample and the transducer, the measurements were performed in water. The transducer employed for the measurements was a 50 MHz focused Olympus PI200573 transducer with a diameter of 6.35 mm and a focal length in water of 5.08 cm. In all cases, the ultrasonic transducer was focused on the surface of the sample. Ultrasonic signals were collected from the specimen by scanning the surface of the specimen at each scanning point, preserving the transient characteristics of the ultrasonic signals. To enhance the signal-to-noise ratio, the collected signals were averaged 128 times. The ultrasonic transducer was excited with a 50 V pulse, and the received signals were amplified by 21 dB. The received signals were sampled using a 14-bit, 125 MHz analog-to-digital converter. A structural diagram of the measurement is shown in Figure 5. After collecting all the data, C-images of the samples were generated, displaying the maximum of the reflected signal in the scanning plane at each scan position. This image enables the analysis of the signal magnitude distribution on the measured sample, indicating the presence of reflectors at various locations on the printed circuit board.

Figure 5. The experimental setup for scanning acoustic microscopy.

2.4. Radiography
Radiography is an imaging technique that uses X-rays to image the internal structure of the object. During measurements, the X-ray source irradiates the test object with a cone beam, and a 2D image at the detector is recorded. The inspected PCB is placed between the radiation source and a detector. The object absorbs a certain number of X-rays. Absorption depends on the density and thickness of the object. A thicker and/or denser area will stop more of the radiation. X-rays pass the object attenuated, and 2D projectional images at the detector are recorded. X-rays ‘see’ a defect as a thickness variation, and the larger the variation, the easier the defect is to detect. The darkness of the image will vary with the amount of radiation reaching the detector through the test object.

When the path of the X-rays is not parallel to a defect, the thickness variation is smaller, and the defect may not be visible. Since the angle between the radiation beam and a linear defect is critical, the orientation of the defect must be well known if radiography is to be used to perform the inspection.

For radiographic testing, a Rayscan 250E computed tomograph was used. Investiga- tions were carried out with a 225 kV microfocus tube. The image was recorded using a 2048 × 2048 flat matrix detector. A schematic of the investigation setup used is shown in Figure 6. The investigations were carried out using a voltage of 150 kV, a current of 130 µA,
and an integration time of equal to 3000 ms. The focal spot using these parameters is 10 µm with a voxel size of 35 µm. However, the resolution achieved is dependent on the size of the investigated object.

Figure 6. Photo of the experimental setup for radiographic testing.

3. Results and Discussion

3.1. Thermography
It could be observed that, in the thermographic image of the additively manufactured board, the vias have the same temperature (dark blue color) as the pads, whereas, in the traditionally manufactured board, the vias have a higher temperature—they have a yellow color. This may indicate that the vias in the 3D-printed PCB have a smaller diameter compared with the traditional PCB. This is suggested by the higher via temperature in the traditional PCB, which implies better heat transmission from the hotplate located beneath the sample. In general, the thermal images were unable to indicate tracks, while the radiographic image showed a higher contrast between the traces and the base material in the additively manufactured board. This indicates that the base material of the 3D- printed PCB has lower emissivity. Thermal cameras have limited spatial resolution in lateral directions and are unable to detect very small defects. This limitation is related to the number of active pixels in the thermal camera’s matrix, as well as the optics and spatial dimensions of the sample being inspected. The results of thermography inspections depend on the thermal conductivity of the materials being inspected. Sufficiently small internal defects may not generate enough heat to reach the surface of the sample and be emitted as thermal radiation. These effects can restrict the detection of defects that are located in deeper layers of the PCB. The materials used in the sample being investigated have varying emission coefficients, resulting in different thermal radiation and making the interpretation of the obtained image more complex. Additionally, the results of thermography inspections are affected by environmental factors such as unstable ambient temperature and random heat flows.

3.2 Radiography
The radiographic images assessment showed that images of the additively manufactured PCB board have higher contrast when scanned with the same parameters. This higher contrast significantly improves the evaluation of the information contained in the image and could facilitate automatic analysis. It is important to note that the radiographic images obtained have the highest resolutions—for the PCB samples inspected, it was possible to achieve a 35 µm resolution. If one could inspect not the
whole board but a part of it, it would be possible to achieve a resolution of up to 10 µm.
Radiographic inspection has two main drawbacks: ionizing radiation poses a risk to human health, and inspection equipment is expensive. Nevertheless, it also has some advantages, such as the ability to provide images with the highest resolution and a quick process. With the inspection parameters set up in advance, the investigation of one PCB can be completed in just 3 s.

3.3 Acoustic Microscopy (SAM)
The ultrasonic images of the traditionally produced and additively manufactured PCBs showed a similar response. However, it was noted that, when using the same inspection setup, the tracks are easier to observe in the traditionally manufactured PCB. The reason may lie in the fact that additively manufactured PCBs use very small amounts of conductive material, which produces material property variations that are harder to detect using the selected inspection setup. However, it is important to note that the provided insights are valid for the particular inspection setup, and changes in inspection parameters may lead to varying results. In general, ultrasonic inspection can be considered the slowest technique, as it requires scanning the surface of the sample and usually submerging the sample in water. The inspection resolution highly depends on the inspection frequency. In this case, by using a 50 MHz frequency, we were able to achieve a 150 µm resolution. By increasing the inspection frequency, the resolution can go as high as 20 µm. On the other hand, unlike thermographic inspection, ultrasonic inspection allows for better visualization of the internal structure, while, in contrast to radiographic inspection, ultrasound provides better capabilities in detecting delamination defects.

3.4 Comparison of Different ND Techniques
In Table 2, we summarize which defects are visible and which are not using different techniques. It can be concluded that radiography allows us to find all artificially created defects, and a 35 µm resolution can be achieved. While the ultrasonic inspection allowed us to achieve a 150 µm resolution, defects 3 and 13 were not visible, namely, a missing track between the SMD component pad and the exposed pad of the component (defect 3) and a missing track between the SMD component pads (defect 13); despite this, the width of both of them was 0.2 mm. This result can be explained by the ultrasound attenuation in the inspected PCBs, where especially high-frequency components tend to be filtered, reducing the actual inspection frequency. Thermography resolved the least number of defects, with a spatial resolution of 0.1 mm according to the lateral directions. With thermography, it was possible to detect all the missing vias (defects 2 and 8), tracks (defect 3), SMD components (defect 5), and pad size reduction (defect 6).

Table 2. Detectability of various types of defects using different techniques in additively manufactured PCBs.

4. Conclusions
In this study, a comparison of different NDT techniques for the evaluation of the quality of PCBs produced using traditional and additive manufacturing technologies was presented. A methodology for investigating changes in the internal structure of PCBs is based on several of the most reliable and widely used technologies, namely, acoustic microscopy, active thermography, and radiography. The use of several nondestructive technologies ensured the reliability of the screening since defects with diverse natures can be detected in this way. Our study shows the following:

4.1 Using active thermography, the contact component solder joints on the PCB surface are visible and can be separated from each other. The spatial resolution according to the lateral directions was 0.1 mm. The thermal images obtained show that the contact component solder joints on the surface of the PCB (various shapes: rectangular and square), as well as the vias, are clearly visible and can be distinguished from each other. Our investigations show that thermography can be used to perform the fast detection of defects in the metallization of the surface contacts (damage to contact tracks, squares, and shielding areas,). The limitations of thermal camera applications are related to the limited spatial resolution and sensitivity of the matrix, the thermal conductivity and emissivity of different materials used in the sample being inspected, the depths of defect locations, and the effects of environmental factors on radiated heat.

4.2 Using SAM, the internal structure of printed circuit boards made using both traditional and Dragonfly LDM technology can be reproduced. The resolution achieved in the sample depends on the thickness of the sample, the smoothness of the surface, the frequency used, and the scanning step. Using a 50 MHz focused transducer and a scanning step of 0.15 mm, contact patches and tracks as small as 0.5 mm can be seen best. In general, the technique was able to detect missing vias, tracks, and SMD pads, as well as incorrect pitch between pads and tracks with width reduction. Under the selected inspection setup, SAM was unable to detect defect 3 or defect 13, which were missing track defects and were too small. However, increasing the inspection frequency and reducing the scanning step would lead to better resolution. On the other hand, such an inspection would be even more time-consuming, as it would require scanning the sample surface with a step size of less than 0.1 mm. In this study, the defects were only considered errors in conductive layer depositions, so SAM was unable to reveal its full potential. It is expected that the presence of delamination between conductive layers and substrates would be perfect for detection with SAM. It should be noted that, in the case of multilayered PCBs, the conductive layers, i.e., the power and ground planes, obscure the reflections from the objects located underneath. In cases where the tracks are located on both sides of the PCB, measurements may need to be taken on both sides of the sample. SAM inspection possesses the longest inspection times and requires the sample to be submerged in water. However, it has a better ability to inspect the internal structure of the sample compared with thermography and has a greater potential for detecting delamination defects compared with radiography.

4.3 High-resolution X-ray images can be obtained using radiography, and resolutions of 100–10 µm can be achieved depending on the parameters and size of the specimen. However, it should be noted that the resolution achieved may vary with changes in the object to be examined (the number of layers in the plate, the density of the materials the plate is made of, or the thickness of the plate)—the resolution achieved with X-rays also depends on the parameters and size of the object being examined. Radiography cannot distinguish the plane in which the objects are visible, but with reference images, it would be possible to quickly assess deviations caused by the manufacturing. Radiographic images of additively manufactured PCB boards have better contrast when scanned with the same settings. This improved contrast makes it easier to evaluate the information in the images and simplifies the automatic analysis. It is important to mention that radiographic images have the highest resolution form of all the investigated technologies. The advantages of radiographic inspection are the ability to provide the highest-resolution images and the speed of the process. With preset inspection parameters, a PCB can be inspected in as little as 3s.

All of the technologies investigated here have their advantages and disadvantages, so if high-reliability products are to be produced, it would be advantageous to carry out tests using different technologies in order to detect the various types of defects and to determine their sizes and depths. Each method used in this study results in the visualization of the internal structure of a PCB. These images of the internal structure could be utilized for automated defect detection algorithms, ranging from simple metrics, such as 2D correlation analysis, to more sophisticated object detection algorithms using artificial intelligence. In this way, the quality assessment process for PCBs could be partly automated.

Copyright: © 2024 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

Click this link for the original source of this paper

Soldering Defects on Immersion Tin and the Impact of the Tin-oxide Layer

Britta Schafsteller, Bernhard Schachtner, Kenneth Lee, Hubertus Mertens, Gustavo Ramos

MKS Instruments – MSD, Atotech Deutschland GmbH & Co  

Dr. Britta Schafsteller

Global Product Manager Selective Finishing

Immersion tin is a final finish highly accepted in the automotive industry and finds increasingly application in the package substrate industry. As due to the immersion reaction the plating thickness of tin is limited, there are concerns that due to the formation of the intermetallic phase during the reflow process, the solderability of the tin layer might be affected. During the assembly process and the formation of the intermetallic phase the free tin is consumed and only islands of free tin remain after the second reflow cycle. Additionally, an oxide layer is formed, and the homogeneity and thickness of the oxide layer is impacted by the reflow conditions and the overall process cleanliness. The interaction of intermetallic phase formation, the amount of remaining free tin and the tin oxide layer will define the soldering performance of the tin layer and the risk of the occurrence of soldering defects. In this paper different failure modes and connected failure mechanisms will be explained. The tin oxide layer is identified to play a crucial role in this interaction and factors are investigated, which impact the oxide layer formation and homogeneity. Various methods are presented to determine the oxide layer thickness and different approaches are studied to modify it. Results are presented that show that with a dedicated solution to modify the oxide layer the risk for solderability defects on immersion tin can be reduced.

I. Introduction
It is the task of the final finish to protect the copper from oxidation and keep the surface active for the subsequent soldering during the assembly process. Immersion tin is one of the most used highly reliable surface finish for soldering applications. The tin layer is deposited by an immersion reaction where the electrons for the tin deposition are provided by dissolution of the underlying copper. Typically, tin layers are deposited with a target layer thickness of 1 to 1.2 µm. Due to the immersive character of the plating reaction, the layer thickness is limited as with increasing tin thickness the exchange reaction between plating electrolyte and copper substrates is slowed down. [1] Typically, 1-1.2 µm thick tin layers are applied on PCBs which is defined by the plating process time and the properties of the tin layer regarding soldering. During the soldering process or thermal exposure of the tin layer, an intermetallic compound (IMC) is formed between copper substrate and tin deposit. On top of the tin layer a tin-oxide layer develops which consists of a mixture of SnO and SnO2.

For the sake of simplicity this will be referred to as SnOx or Sn-Oxide in the following. The IMC, the remaining tin and the Sn-Oxide layer determine the soldering properties of the immersion tin finish. This has been studied and described by e.g., T. Hetschel et al. in 2009. [2, 3]

During the growth of the IMC the free tin is consumed which leads to remaining island of tin between IMC and Sn-Oxide layer. During the soldering process when the free tin becomes liquid, this can cause stress to the Sn-Oxide layer which if the Oxide layer is inhomogeneous may lead to cracks in the Sn-Oxide layer. In these areas the liquid tin can reach the top of the layer surface leading to cosmetic defects and in the worst case to poor wettability.

II. Failure modes of immersion tin soldering
As described in the introduction during the assembly process and the thermal reflowing of the tin layer, the IMC and Sn Oxide layer formation leads to a change of the layer properties. Figure 1 summarizes the different conditions that the layer exhibits at the individual aging stages.

Figure 1: IMC formation during 1st and 2nd reflow of an immersion tin layer

During the first reflow cycle a Cu/Sn IMC is formed which mainly consists of Cu6Sn5 and small shares of Cu3Sn. [4] On the assembled side the IMC is formed directly with the solder while on the unassembled side the IMC is formed between copper and the immersion tin layer. In the second reflow cycle the IMC further grows and consumes more of the remaining free tin.

Soldering defects that appear during the assembly of immersion tin layers are very likely related to contaminations which are brought in prior, during or after the tin plating process. Depending on when the contamination happens, different defects can be observed:

- Non-wetting is often related if the tin surface is contaminated which acts as a physical barrier to the solder.
- De-wetting appears if the liquid solder recedes after the wetting and is often related to inadequate cleaning or an inhomogeneous Sn-Oxide layer.
- Self de-wetting can be observed if the liquid solder penetrates the oxide layer during the reflow cycle and agglomerates on the Sn-Oxide surface.

For the two latter defects the homogeneity of the Sn-Oxide layer is crucial and contaminations of copper before the tin plating or condensation of organic components during the reflow can cause these issues.

If residues on copper remain on the surface and are not properly removed before the tin plating process, the are incorporated in the tin layer and during reflow and IMC formation can migrate to the layer surface. This can affect the stability of the Sn-Oxide layer and lead to cracks where liquid tin can penetrate and reach the layer surface causing self de-wetting. A simple test how contamination of the copper surface can impact the IMC formation is shown in Figure 2:
Figure 2: Test strip after successive tin stripping with and without contamination by fingerprints

In this test, fingerprints were applied to copper coupons and afterwards plated with immersion tin. After the tin plating the coupons were heat-treated for 1 hour at 155°C. By successive stripping in nitric acid the tin layer was removed stepwise down to the IMC. It can be observed, that in the fingerprint areas more IMC is remaining which indicates, that the IMC formation is accelerated in the areas of contamination.

The thickness of the Sn-Oxide layer is also defined by the atmosphere being applied during the reflow aging. Directly after tin plating the Sn-Oxide layer thickness is determined to be between 1-2 nm. Depending on the reflow atmosphere this increases to 5-6 nm in Nitrogen or up to 9 nm in air. One potential root cause for soldering defects can be the re- condensation of organic components of the solder mask or base material during the reflow process. These condensates can interact with a weak Sn-Oxide layer and by that lead to self de-wetting defects.

Figure 3: appearance of tin layer after 2nd reflow with varying reflow conditions

In figure 3 a test is shown, where different immersion tin plated samples were subjected to a reflow cycle. The solder mask of half of the samples was treated with a UV treatment to achieve a better cross linking of the organic components and by that a reduced risk for evaporation of volatiles. [5] After the tin plating the samples were process through two reflow cycles at air and at nitrogen atmosphere. The images in figure 3 show, that the worst appearance is observed with the coupon which is not UV-treated and reflowed in nitrogen atmosphere. The sample with the best and defect free appearance was subjected to UV-treatment and went through a reflow under air. The result indicates, that:

1. the air reflow supports the growth and strengthens the Sn-Oxide layer.
2. the UV-treatment can mitigate the evaporation of volatiles in the soldermask to reduce the re-condensation on the immersion tin layer.

In consequence a combination of both leads to the best appearance and defect free appearance of the tin layer.

III. Factors that impact the Sn-Oxide layer formation
The Sn-Oxide layer forms as soon as the tin layer gets in contact with air. It consists of a mixture of SnO and SnO2 where SnO is more dominant as it is energetically favored. The oxide layer that forms directly after tin plating after exposure to air is typically 1-2 nm thick. Over time the Sn- Oxide layer slowly continuous to grow leading to a thickness of about 5nm after five years at room temperature. Higher temperature and humidity can accelerate the oxide formation. [6] The Sn-Oxide layer thickness values presented in this study were determined by SERA (sequential electrochemical reduction analysis) and confirmed by TEM (transmission electron microscopy) measurements.

Figure 4: TEM image of the Sn-Oxide layer to back the SERA result

The SERA-measurements were performed varying the measurement time between 50 and 200 seconds on seven spots per condition. The measured potential was plotted versus the current density and based on the turning points the Sn-Oxide thickness can be determined. To determine the impacting factors on the Sn-Oxide growth different plating conditions were adjusted:

- variation of drying time after immersion tin plating
- variation of posttreatment after immersion tin
- thermal and humidity aging

Figures 5 to 7 show the Sn-Oxide layer thickness as determined with the different conditions:

Figure 5: Impact of drying and storage conditions on SnOx formation

For a variation of the drying conditions after the tin plating process the drying was done using a) compressed air, b) heater at 65°C, c) oven at 85°C. After the drying half of the panels was stored in vacuum package while half of them were stored openly for 7 days. While the drying procedure has a negligible impact, the storage conditions show significant differences. While the vacuum-packed panels exhibit only a slight increase of Sn-Oxide thickness, the panels stored in air show a significant increase of up to 50%.

Figure 6: Impact of humidity aging on SnOx formation

A similar trend is observed if the panel is exposed to humidity aging for eight hours at 72°C/85% relative, humidity. In this case the Sn-Oxide layer thickness increases by almost 100% compared to the reference sample.

A smaller but still significant impact can be observed after thermal treatment. While a significant growth is observed in the first two hours of heat treatment, further exposure do not lead to significant changes.

Figure 7: Impact of thermal aging on SnOx formation

Beside physical factors to increase the oxide layer formation also chemical posttreatment solutions have been evaluated. It can be shown that a tailored chemical post-treatment step after immersion tin can lead to a significant increase of the Sn-Oxide layer thickness of about 60 to 80%. 
Figure 8 summarizes the results that can be achieved with different post-treatment concentrations, dwell times and temperatures.

Figure 8: Impact of a chemical posttreatment after Immersion tin on the Sn-Oxide formation

IV. Sn-Oxide layer impact on self de-wetting
In order to prevent self de-wetting defects on immersion tin according to the theory explained in section II a thicker Sn- Oxide layer is assumed to be beneficial. A thicker Sn-Oxide layer should help to prevent discoloration and shiny appearance after exposure to the second leadfree reflow cycle. Therefore, test coupons plated with immersion tin were immersed to the post-treatment solution and investigated after reflow treatment. In figure 9 the appearance of a test panel is shown, that was immersed to the post-treatment solution and reflowed in nitrogen atmosphere. A clear demarcation line can be identified between the 
treated and untreated immersion tin layer. While the treated tin layer surface appears white matte, the no treated surface shows a dark and shiny appearance caused by self de- wetting.

Figure 9: Appearance of the ISn layer with and without post- treatment

Comparing the appearance after nitrogen reflow and after reflowing under air it can be confirmed, that the additional chemical post-treatment can prevent the dark and shiny appearance. Even though the risk for the defect is reduced when the reflow is processed in air, the appearance can further be improved for air as well as for nitrogen atmosphere.

Figure 10: tin layer appearance with and without post-treatment

To confirm that the increased Sn-Oxide layer thickness does not have any negative impact on the solder wetting performance of the immersion tin layer, solder spread tests have been performed. Senju M31 solder paste was used to apply solder dots on the tin layer and reflow the solder through a reflow oven. After the reflow treatment the wetting angle of the solder spread was determined. A low wetting angle indicates good solder wetting. The immersion tin layer was exposed to the post-treatment for varying dwell times from 0 to 60 minutes correlating to Sn-Oxide layer thicknesses between 1.3 and 2 nm. For all tested conditions similar wetting angles can be observed. By that it can be confirmed, that the post-treatment has no negative impact on the solder wetting of the immersion tin layer.

Figure 11: solder spread testing of an ISn-layer with and without post-treatment

III. Conclusion
The properties of an immersion tin layer regarding appearance and solder wetting after thermal or reflow aging are determined by the formation of the intermetallic compound and the Sn-Oxide layer. With increasing thickness of the intermetallic compound, the remaining free tin volume is reduced leading to localized stress once the tin becomes liquid during the 2nd reflow cycle. The homogeneity and robustness of the Sn-Oxide layer is therefore important to prevent it to break and liquid tin to penetrate and wet the surface. Thermal treatment and reflow under air can accelerate the oxide layer growth while vacuum packing and reflow under nitrogen atmosphere slows down the Sn-Oxide formation. To strengthen the oxide layer by purpose chemical post-treatment can be applied which mitigates the risk for self de-wetting defects and dark and shiny appearance after reflow aging. It was confirmed that this post-treatment can accelerate the Sn-Oxide formation without having a negative impact on the solder wetting of the immersion tin layer.

References
[1] M. Jordan, Die Elektroabscheidung von Zinn und seinen Legierungen,
Chapter 7, Egon G. Leutze Publishers, 1995
[2] T. Hetschel, Alterungsverhalten und Lötbarkeit der chemisch abgeschiedenen Zinn-Leiterplattenoberfläche Technische Universität Dresden, Elektronik und Informationstechnik, 2009
[3] T. Hetschel, K-J Wolter, F. Philipp, Wettability Effects of Immersion tin Final Finishes with Lead Free Solder, 2nd Electronics System Integration Technology Conference Greenwich UK, 2008
[4] R. Nichols, S. Heinemann, Soldering immersion tin, IPC APEX 2017
[5] R. Nichols, G. Ramos, L. Nothdurft, B. Schafsteller, Is it possible to use markers to select the right soldermask to optimize the yield of your selected finish?, SMTA impact 2015
[6] Britton, S., & Bright, K.: An Examination of Oxide Films on Tin and Tinplate. Metalurgia, 1957

Foundation Course 15th - 18th April 2024

Chester University

Emma Hudson

ICT Technical Director

For the 2024 ICT Foundation Course we had the pleasure to welcome 25 students from 13 different companies, all keen to learn more about the PCB manufacturing processes.
The course started at the Merlin Circuit Technology facility in Deeside, who generously welcomed us for another year. The course starts on the Monday morning with two lectures, followed by a lovely lunch, a factory tour, and two further lectures….no breaking them in gently!

Merlin Circuit Technology facility in Deeside

Once the lectures were done, we all moved on to the course hotel, a couple of miles away from Chester University, our venue for the next three days. It’s been a tradition since the first course in 1980 that we all gather together on the first night for a team dinner, allowing everyone to get to know each other a little better in a more relaxed environment. With some old hands in the industry being a part of the dinner, the students got to hear some of the tales from years gone by (don’t worry, we didn’t name any names!). It was just the start of the networking during the course, and it was very positive to see relationships being built which will hopefully last long beyond our time in Chester.

For the next three days of the course, we based ourselves at the hospitable Chester University who not only provided us with a superb lecture theatre but also some wonderful catering, I don’t remember lunches like that when I was at university. It was so good that at the end of the course, the catering team were welcomed into the lecture theatre for a round of applause from all in attendance.

Neil Chamberlain - Polar Instruments

Andre Bodegom - Adeon

All our students were welcomed into the Institute as Associate Members whilst attending the course. Bill Wilkie (Technical Director at the time of the course, now our new Chairman) presented all of our new members with their certificates, although one did manage to dodge the photo but I did get him on the group shot (just hiding behind the Foundation Course banner).

There are so many people involved in making the course the success it is, so our thanks go out to all of our students, their companies who send them, all of our 16 lectures who give their time for free, and Merlin Circuits for hosting day 1 along with all of the staff that were involved in facilitating the factory tour.

2024 Delegates 

There is one special set of thanks this year for Mr William Wilkie, more affectionately known to us as Bill. This was Bill’s last year of organising the Foundation Course, retiring as Technical Director at the completion of it. Bill makes the organisation of the course seem effortless but having been there for the week with Bill, I now appreciate just how much time and effort he takes to ensure that the ICT Foundation Course has been and continues to be a success. I only hope that I can live up to his mantle when it comes to our 2025 Foundation Course.

Emma Hudson, Technical Director

A few comments from the delegates:
Course was better than I thought. Lovely bunch of people on the course too. Would highly recommend the course to my colleagues.
Fantastic run course. Thanks a lot :)
Thanks for the course. As a new in PCBs, I had chance to meet with the people in the PCB business, it contributed a lot to my PCB knowledge.
I had no knowledge prior to the course, now I do….thank you.
Thank you for having me, I have thoroughly enjoyed the course. It has been a wonderful experience! Loved the lectures!
Really good experience.

It is with a heavy heart I have to share the news we have lost another member of the old PCB Industry Characters. I’m afraid Roy Polson lost his battle with an asbestos related lung cancer in the early hours of this morning.

Steve Jones and I saw him on Friday morning for a very short visit but we managed to have a laugh and reminisce about some of the stories from the old days. It made him smile, he threw some mud back at us.

He started his career at Prestwick Circuits when the industry was in its infancy before being part of the success at Manchester Circuits. He then had a stint at Thomas Walters during a massive growth period leading to DDI purchasing the business.

He and Pat enjoyed a great retirement in Spain up until recently when they moved back home to the West Coast of Scotland. He is now out of pain and no longer suffering.

My thoughts as I’m sure yours are with Pat, Kirsten, Chris and the rest of the family.
RIP Roy

Anthony Jackson 
9th July 2024

I didn’t know Roy that well when he was Sales Director at Prestwick. We’d nod in passing through airports and at the annual Prestwick Golf Tournament, but that was it. When he became MD at Manchester Circuits, he ‘invited’ me to a meeting he was holding at BA Systems and I felt I had to go even if it was a Saturday Morning! It was a biggish conference room and packed out. Roy wasn’t a big lad, but when he opened the meeting, he owned that room and everyone in it, captivating, powerful, fearless – a real captain of Industry.

I had a new respect for Roy after that meeting and he always made time for a chat. We shared a dinner table at Crieff and as you can imagine, that was a lot of fun.

This was a time of great flux and upheaval in the industry and Roy went on to become a senior figure in Thomas Walter and the DDI group. Even in a team of memorable characters, Roy was a giant personality in the Market-dominant companies of the day. He was a one-off and he’ll be sadly missed

Bill Wilkie

Lee Corfe

Inkjet Development Manager

Electra Polymers is excited to welcome Lee Corfe as the newest addition to Electra’s inkjet team. With an impressive background and a wealth of experience in high-performance functional inkjet materials, Lee brings a fresh perspective and a dynamic skill set to our organization.

Lee Corfe joins us as Inkjet Development Manager and will play a pivotal role in this exciting growth area. With a passion for inkjet formulation and innovation, Lee is poised to make significant contributions to our team's success.

Kamal Berberi

General Manager

Congratulations to Kamal Berberi on his Promotion to General Manager at Exception PCB.

Steering Exception PCB Ltd as the General Manager, my focus is on elevating operational performance through strategic leadership and Lean Six Sigma expertise. My journey in the electronics industry has honed a robust skill set in strategic marketing management and quality management, enabling the delivery of superior printed circuit board services with unwavering commitment to efficiency and customer satisfaction.

Alun Morgan

Jiva Materials

Steve Driver

CEO Jiva Materials

Jiva Materials have appointed Stephen Driver FInstCT as CEO.This is following the decision of Jonathan Swanston to retire. Jonathan has been an invaluable and dedicated leader during his time as CEO.

Our stakeholders and partners can be assured that Steve and the rest of the team will continue to drive Jiva forward. All of us here at Jiva wish Jonathan a very happy retirement and thank him for his service.

Leigh Allinson

Ventec Giga Solutions

Marc Ladle

Ventec Giga Solutions

Andrew Norton

June 21st 2024
Our penultimate day before arriving home after 12 months at sea. As I write it is 3:30am and I’m on watch alone enjoying a clear sky and dawn already starting to appear. Galatea is sailing herself downwind in near perfect conditions at a heading directly for home in Cowes, Isle of Wight. Magical. We should arrive Saturday night.
What an amazing experience Muriel and I have had. We are both looking forward to arriving back, to see our friends and have the comforts of home.
Over the last year we have visited so many places, met so many lovely people and shared some incredible experiences. We have made new friends who I’m sure will become part of our life. You know who you are!
All this I could not have done without Muriel Lismonde. She has not only supported my passion for sailing but embraced it. She has been incredible to get through the sometimes tough sailing conditions that we have had (especially in the last few days). Lucky me!

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Section 8

Industry News

New challenge set to put printed circuit boards to the test

When national security organisations use electronic equipment in sensitive environments, they must be sure every element has been properly assured.

In its latest challenge, HMGCC Co-Creation wants companies and academia to apply to a five-month, funded project, aimed at developing ways to robustly assure printed circuit boards (PCBs).

HMGCC Co-Creation is a pilot initiative which involves reaching out to academia and wider industry to help find solutions to national security challenges.

The challenge is looking for innovative methods to provide assurance that PCBs will function where and when they are most needed.

More details about the challenge are available from our collaborators. For the full list of collaborators please visit our Co-Creation page.

Hannah Whitmore, EHS & Sustainability Manager at Amphenol Invotec collects Award in recognition for our excellence in water consumption reduction across our UK sites in Telford and Tamworth.

By the end of this year we will have reduced our usage by 17.7%. It is thanks to the hard work and collaboration of our staff we have achieved this goal in 2 years and we are proud to have received this sustainability award.

Electra Invests in new soldermask Lab Equipment!

We're thrilled to announce our latest investment in inkjet-related laboratory equipment! This game-changing technology will empower Electra to push the boundaries of thermal storage and thermal cycling for Inkjet soldermask, taking our innovation to new heights!
With the newly installed equipment, we are now equipped to conduct rigorous testing for reliability, ensuring best in class performance and quality. Our commitment to excellence drives us to explore new possibilities and set industry standards.

We are pleased to announce that our sister company TWM Technology have joined the EPIC Centre in Torbay, Devon.

The EPIC Centre is home to the Torbay Hi-tech cluster and is a regular host of IMAPS events. This purpose-built centre has been designed to accommodate Tech Companies in the Torbay area. These companies have been collaborating together and also with technical colleges and universities in the Southwest and further afield. This has had a positive impact on promoting sectors within the high growth area of technology, photonics, RF and Microwave. This includes education and helping to sustain the historical presence and importance of this part of the country in cutting edge technologies, both now and for many years to come.

We are really looking forward to getting involved with the rest of the tenants at the EPIC centre and with the local business community.

From the group’s point of view, we are gaining access to some cutting-edge technology and equipment including a Class 7 cleanroom and some state-of-the-art inspection and analysis equipment. We look forward to further developing and perfecting our void free soldering processes and sharing ideas, expertise, inspiration, and experience.

GSPK Circuits' Chairman and Directors celebrated a significant milestone in the company's history as a market-leading PCB manufacturer and technology innovator.

Back row left to right: Martyn Gibson, Operations Director; Steve Lloyd, Managing Director; Andrew Grisbooke, Chairman; and Ian Kenyon, Sales Director.

From left to right, the front row is Jonathan Calver, Technical Director; Brent Pemberton, Financial Director; and Anthony Lloyd, Supply Chain Director.

Merlin Flex has installed & commissioned a UV laser cutting machine from Beyond Laser. This new investment, supplied via Technic in the UK, has a twin bed which significantly increases capacity plus provides additional capability of laser cutting long flex up to 1.4M in a single length.

Mark Merifield, Merlin Flex MD, says “the new laser machine has been a great addition to our existing laser department and I would like to thank the management and engineers of both Technic and Beyond Laser for their great support and work on getting this machine installed and fully running in mainstream production on all of our flex & flex/rigid products”.

This new Beyond Laser machine is the 3rd UV laser machine at Merlin Flex and sits alongside it’s 2 existing Schmoll UV Laser Flex machines.

Merlin Circuit Technology Limited is pleased to announce they have been awarded Nadcap Merit status. Matthew Beadel (MD) stated this is a great achievement by all of our staff and demonstrates Merlin’s ongoing commitment to produce PCB’s to the highest quality levels for all of our current and future customers.

Jack Herring Chief Product officer of Jiva Materials and Paul Goodfellow, Managing Director of Minnitron Ltd sign the Preferred Partnership Agreement.

Today (22/05/2024) Jiva materials and Minnitron Ltd signed a Preferred Partnership Agreement for the manufacture of Soluboard – the worlds’s first fully recyclable Printed Circuit Board laminate.

Jack Herring the inventor of Soluboard signed an historic agreement with Minnitron Ltd. This agreement solidifies the agreement that the two companies have been enjoying over the last four years for Minnitron to be the preffered manufacturing partner for the Soluboard recyclable PCB laminate.

Paul Goodfellow said “This agreement allows both companies to really push forward the development and commercial viability of Soluboard and we look forward to working with Jack and Jiva for many years to come”.

Our wet processing and administration extension is gathering pace. For those of you who like watching buildings go up, here is today’s picture of the start of the cladding installation. The cladding panels are 125mm thick double sided metal cladded foam. Next week, the solar panels get installed.

Membership News

Emma Hudson
Technical Director and Membership Secretary, ICT.

New Members

Section 11

ICT Council Members

Council Members

Bill Wilkie (Chairman) Emma Hudson (Technical Director, Hon Sec, Membership & Events), Andy Cobley, Steve Payne (Hon Deputy Chairman), Chris Wall (Treasurer), Richard Wood-Roe (Journal Editor & Web Site), Jim Francey, Martin Goosey, Pete Starkey, Francesca Stern, Mat Beadel, Brian Morgan, Leigh Allinson. 

Section 12

Editors Notes

The ICT Journal

Richard Wood-Roe
Journal Editor

Instructions / Hints for Contributors

1. As it is a digital format the length is not an issue. Short is better than none at all!

2. Article can be a paper or a text version of a seminar or company presentation. Please include data tables, graphs, or powerpoint slides. We can shrink them down to about quarter of a page. Obviously not just bullet points to speak from.

3. Photo's are welcome.

4. We would not need  source cross references

5. Title of presentation Of course! Date, Job title of Author and Company represented.

6. An introductory summary of about 150 words would give the reader a flavour of what it's all about.

7. Style we don't want out and out advertising but we do recognise that the author has a specialism in the product or process that will include some trade promotion. Sometimes it will be a unique process or equipment so trade specific must be allowed.

8. Date and any info relating to where or if this article may have been published before.

9. We can accept virtually any format. Word, Powerpoint, publisher, PDF or Open Office equivalents. 

10. Also, to make it easy, the author can provide a word file to go along with his original powerpoint presentation and I/we can merge it together and select the required images. 

11. A photo of author or collaborators.

I really do look forward to receiving articles for publication.

Richard Wood-Roe

This email address is being protected from spambots. You need JavaScript enabled to view it.

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