The Journal of |
Section 1 | Editors Introduction |
Richard Wood-Roe |
In this issue of The Journal we have included an update to the IPC alert about microvia reliability from Happy Holden. There is a paper outlining the optimisation of process parameters for microvia processing from Bill Bowerman of Alpha Macdermid. Daniel Schulze of Dyconex has provided a fascinating contribution detailing the benefits of thin materials for space saving and reliability. Computer Aided Engineering Simulation for Production Proofing PCB Copper Plating is the subject of a paper from Robrecht Brelis of Elsyca. We are grateful to Pete Starkey for his write up of the recent ICT evening seminar that was held in Meriden, West Midlands. In the members news section we report on the sad passing of Bill Miller, a founding father of the UK PCB industry. The members update section shows a large increase in members from the successful on-line engineering course. This course will be available again soon via our web site. Finally the industry news section highlights the activity of some of our members. |
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Section 2 | Calendar of Events | |
Bill Wilkie |
2023 |
Details |
March 7th | ICT AGM and Spring Seminar at Meriden. Council Meeting – Starts at 12 noon, Fab Group Meeting starts at 14:30, AGM/Seminar starts at 18:00 – to be followed by a buffet. Manor Hotel Room Rate - £100/night B&B at ICT Rates |
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April 24-27th | Annual Foundation Course, Chester | |
2022 | ||
Nov 29th | Evening Seminar at Meriden Preceded by Council Meeting and Fabricator Meeting. | |
September 7, 14, 21, 28 and October 5, 12, 19, 26 |
On-line Engineering Training with Happy Holden. Each session is from 4pm to 5pm | |
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Section 3 |
IPC Warning About Microvia Reliability for High Performance Products Editors Note: It is recognised that this alert was issued some time ago but it has been included in this issue of The Journal to ensure that members who may have missed it are informed. |
Happy Holden |
Hopefully, by now, you have read the full Press Release from the IPC on March 6, 2019, about the warning of field and latent failures of high-profile HDI boards. IF not, the complete press release is available on I-Connect 007. [1] DON’T PANIC! Let me explain the background of this warning. For the last few years, a few OEMs have experienced a latent defect in their sophisticated HDI multilayers even though screened with our best available incoming inspection and test methodologies. This defect caused failures observed in: • Post-Reflow In-Circuit Test After much work and investigations by these OEMs, and with coordination with the D-32 Thermal Stress Test Methodology Subcommittee, the IPC issues a new test method for thermal stress, (IPC-TM-650, Method 2.6.27A) and thermal shock (IPC-TM-650, Method 2.6.7.2). The Method 2.6.27 calls for the test vehicle or coupon to be subjected to a normal solder paste reflow profile to reach a peak temperature of 230 degree C or 260 Degree C while under connection to a 4-wire resistance measuring unit for six (6) full reflow profiles without the increase of resistance of 5%. The daisy chain in the test coupon needs to be composed of features used in the actual circuits. This has allowed these OEMs to detect the latent microvia failures and protect themselves from possible defect escapes. But finding the Root Cause of this latent HDI failure has been elusive. So, in early 2018, the IPC organized a select group of industry experts, under the supervision of Michael Carano, to investigate this situation. Later in 2018, this group was named the IPC V-TSL-MVIA Weak Interface Microvia Failure Technology Solutions Subcommittee. I am a founding member of this group. But let me emphasize, During the past year, we have met and gone over test data, microsections and experimental results. Here is what we KNOW: • The defect manifests itself as a fracture at the metallurgical interface of a microvia to the copper layer below it or to another microvia below it. (see Figure 1) FIGURE 1. The WMI latent defect observed after six reflows of 230 OC. [used with permission][4] • First occurrence of the product-level failure detected (stacked microvias) 2010. FIGURE 2. A complex HDI qualification coupon (3-8-3) with both stacked and staggered microvia structures. [used with permission] [4] • Product-level failures are unpredictable (in-process, storage or filed) FIGURE 3. Reflow profile and 4-wire resistance of a 4+N+4 stacked microvia structure opening at only 224.6C and closing at 184C on cooling down. Subsequent room temperature testing and thermal cycling testing indicated no defect. [used with permission] [4] • Although the committee developed an FMEA for microvia defects, only this one WMI is our focus. To further read about the WMI Committee and our findings, there is a report available from our APEX 2019 WMI OPEN FORUM[2] and a White Paper was published by the committee, IPC WP-023 “Via Chain Continuity Reflow Test: The Hidden Reliability Threat- Weak Microvia Interface.” Available from the IPC Bookstore. REFERENCES |
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Section 4 | Process Improvement Strategies for Weak Microvia Interfaces
William Bowerman, Jordan Kologe, Rich Bellemare and Warren Kenzie MacDermid Alpha Electronics Solutions |
Bill Bowerman |
Abstract
Figure 2 – UV-CO2 laser drilled microvias shown after shown after UV clean, plasma, and desmear.
Figure 3 – The effect of chemical pre-etch on resinous debris.
Figure 4 – 2 Level DOE results for UV clean, desmear cycle, and flash plating impact on 50x reflow failure rate.
Figure 5 – Top, main effects plot for solution movement DOE. Bottom, copper grain structure at base of target pad rating system examples.
Figure 6 – Top: Experimental results that display the effect on microvia aspect ratio and diameter on grain structure quality. Bottom: Example of plated electroless copper at the via target pad and the rating of grain structure.
Figure 7 – Study: Adjustment of the control levels for the specific gravity of the electroless copper bath for HDI. A study was done, selecting panels run at various sites around the world to see the effect the grain structure had on simulated reflow testing per IPC 2.6.27. Figure 8 shows the electroless copper grain structure at the via target pad for the various sites A-E. The same electroless copper formulation was run at different sites for A, B, C and D. Site E was a different electroless copper formulation. Sites A and B show the ideal angular grain structure. Sites C and D show a dense structure but not ideal. Site E appeared porous and cauliflower like. Sites A and B passed 24 OM cycles as the censor point while the other panels had some level of failures before 24 cycles. Figure 8– Electroless copper grain structure plated at various sites around the world.
Figure 9 – Etch chemistry impact on roughness and topography of the underlying substrate.
Figure 10 – 3+N+3 Stacked microvias showing continuous grain structure and strong layer to layer bonding. Recrystallization had formed a continuous grain structure indicating strong layer to layer bonding. Lack of recrystallization across the various copper interfaces can be attributed to several factors. Recrystallization can be interrupted by a macro-rough surface on the target pad, from recast copper, from a layer of oxidization on any interface during metallization, dry film or developing residues, or by a non-epitaxial copper structure that did not follow the orientation of the substrate.
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Section 5 |
Ultra Thin Base Materials Take PCB Manufacturing to the Next Level Daniel Schulze |
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Daniel Schulze Application Engineering Manager - Dyconex |
Almost all markets are experiencing increasing demand for smaller and thinner electronic devices. Today’s mobile devices are small enough to fit in a watch, and the aerospace and automotive industries desire smaller and lighter devices to lower fuel costs and reduce emissions. Likewise, the medical industry needs wearable sensors, implantable devices, and handheld instruments that are small and lightweight. Manufacturers of the printed circuit boards (PCBs) that are at the heart of these electronic devices have been making them more compact and lighter primarily by decreasing the size of the copper features and board materials. Extremely thin base materials are making it possible to take miniaturization beyond what was previously possible without compromising reliability or performance. Figure 1. Evolution of pacemakers. Image courtesy of Biotronik. With thinner base materials, less plated copper is needed to fill via connections. This automatically results in thinner copper layers and, therefore, lines/spaces with smaller resolutions and a reduced interconnect footprint. Figure 2. 6-layer stack-up with standard flex material compared to 6-layer stack-up with ultra-thin base material. Flex systems are used in hearing aids to ensure all the necessary electrical components can be housed within a package that fits in the ear canal. In this case, the circuit board is assembled flat with the integrated circuits, resistors, and capacitors and then folded to reduce the overall footprint. Figure 3. From flat substrate to folded package. Ultra-thin flexible substrates also allow better bending. This means the PCBs can be bent with smaller bend radii to achieve even smaller volumes. A comparison is shown in Table 1. The improved bending makes ultra-thin flexible materials ideal for making cables that require dynamic bending, as in robotic arms.
Table 1. Comparison of minimum bend radii according to IPC-2223 5.2.4 Today, the outer layers of a multilayer flex system typically measure 12 µm for the polyimide and 12 µm for the adhesive. The new Flexible Resin Coated Copper (FRCC) material available offers 3 or 5µm thick polyimide outer layers combined with a minimum 17 µm thick adhesive layer.
Figure 4. Cu clad polyimide laminate.
Table 2. Characteristics of FRCC materials.
Figure 5. Standard 4-layer flex system vs. ultra-thin 4-layer flex system
Rigid Systems
Figure 6. 6-layer stack-up with standard rigid material compared to 6-layer stack-up with ultra-thin base material.
Table 3. Comparison of design features for 6-layer systems
Figure 7. 6-layer rigid stack-up with ultra-thin materials. The coefficient of thermal expansion of the rigid substrate is one of the most important properties for chip packaging substrates. If it is not matched well with the silicon die, it can lead to cracks that adversely affect packaging production and the assembly of the components onto the substrate. Problems with thermal expansion can even lead to failures during device use. Ultra-thin substrate materials also need to have very good high-frequency properties to achieve the requirements of today’s high-speed telecom applications.
Table 4. Characteristics of advanced ultra-thin rigid material.
Conclusion |
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Section 6 |
Computer Aided Engineering Simulation for Production Proofing PCB Copper Plating Robrecht Belis, Elsyca, Belgium |
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Robrecht Belis |
Maximizing production yield is vital for PCB manufacturing. PCB Layout before and after copper balancing (Right picture – black areas represent added dummy copper features) Existing DFM tools do not allow to assess finished copper thickness CAE simulation technology empowers designers to optimize PCB copper plating Predicted copper distribution before and after optimisation During the electroplating process, the PCB substrate is submersed in a tank with an electroplating bath and anodes. As direct current always seeks the path of least resistance between the anodes and the cathode, PCB edges and areas with a sparse active copper surface attract more than their fair share of current compared to areas with a high number of traces, through-holes, vias or pads. Due to this current crowding effect, more copper deposits onto the PCB along its edges and in areas with a sparse active copper surface. That explains why finished copper thickness typically shows an unwanted variation across the circuit board. No two pcb's are produced the same way Even if a PCB panel only contains identical board designs, the copper plating process does not deliver the same finished copper thickness for each PCB. Copper balancing reduces differences between circuit boards on the same panel. To mitigate this problem, CAM engineers can modify the panel layout, or they can apply copper balancing to thieve current from areas that attract more than their proper share of current. Adding dummy copper features near the panel edges and in between individual boards achieves a more uniform distribution of finished copper thickness across the entire panel. Auto-intelligent copper balancing lets PCB manufacturers deliver better boards at a lower cost.
Ultimately, CAE simulation lets CAM engineers deliver a better service to production. In particular, product testing can focus its resources on the most critical elements. CAE simulation technology also allows process engineers to fine-tune copper plating production settings. Typical PCB Electroplating Line Elsyca, Belgium Tel: +32 16 474960 |
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Members News |
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Bill Miller - Prestwick Circuits Ltd. Bill has already had an obituary placed in the Times Newspaper, but as a Fellow of the Institute, (Membership Number 556), it is fitting that we include our own thoughts in our Quarterly Journal. The Times obituary is available here. |
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Andrew Bunt |
IPC CIT Certification Andy Bunt is a now a Certified IPC-A-600 Trainer and will start an internal training programme for employees soon. We would like to congratulate Andy for his work achieving this certification. |
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Industry News |
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Adeon Technologies BV |
ACB Group invests in new Flying Probe System The ACB group is one of Europe’s largest independent manufacturers of highest technology printed circuit boards. The group consists of manufacturing facilities at Dendermonde (Belgium), Atlantec and Cibel (France) Read more... |
Amphenol Invotech | Environment and Sustainability An interview with Hannah Whitmore Amphenol Invotec’s new Head of Environment and Sustainability Read more... |
GSPK Circuits | Innovative Copper Coin Thermal Solution A copper coin is a solid piece of copper that is put onto or into the PCB, usually beneath the component or components that require cooling. When compared to a collection of thermal vias copper coins will produce roughly twice the cooling. Additionally, the copper coin can offer direct contact between the heat-generating component pad and the heat sink in place of thermally conductive material. Compared to other conductive dielectric prepregs, copper has thermal conductivity that is typically 50–200 times better. Read more... |
Minnitron Ltd. |
Family Business Awards |
Newbury Electronics Ltd | Managing Director of Newbury Innovation Conor La Grue, has been appointed to the position of Managing Director of Newbury Innovation, the design division of Newbury Electronics Ltd. Newbury Innovation has grown significantly over the last 3 years and is now a major business unit within the Newbury Group. Read more... |
Southern Manufacturing | Southern Manufacturing & Electronics show will be held from 7-9 February 2023 The annual Southern Manufacturing & Electronics show is a firm favourite on the calendar. Aerospace Manufacturing takes a closer look at what visitors can expect to see at the Farnborough Exhibition Centre from 7-9 February 2023. |
Taiyo |
Taiyo Circuit Automation European Distributor for Shur-Loc Products Taiyo Circuit Automation today announced a new partnership with Shur-Loc Fabric System. This partnership will combine Taiyo Circuit Automation world renown range of solder mask equipment with Shur-Loc’s unique screen making system. Read more... |
Trackwise Designs plc | Quality Assured at Trackwise Designs plc Trackwise is delighted announce the successful completion of their AS9100/ISO9001 surveillance audit. The surveillance audit is a biannual process where the QMS processes are audited. This is to demonstrate “the ability to consistently provide products and services that meet the customer and regulatory requirements” Read more... |
Ventec International Group |
High Thermal Conductive Metal Base Laminate |
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Membership News |
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New Corporate Members
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New Member
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New Associate Members
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ICT Council Members |
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Council Members |
Emma Hudson (Chair), Andy Cobley (Past Chairman), Steve Payne (Hon Deputy Chairman), Chris Wall (Treasurer), William Wilkie (Technical Director, Hon Sec, Membership & Events), Richard Wood-Roe (Journal Editor & Web Site), Jim Francey, Martin Goosey, Lynn Houghton, Lawson Lightfoot, Pete Starkey, Francesca Stern and Bob Willis, |
Editors NotesThe ICT Journal |
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Richard Wood-Roe |
Instructions / Hints for Contributors 1. As it is a digital format the length is not an issue. Short is better than none at all! 2. Article can be a paper or a text version of a seminar or company presentation. Please include data tables, graphs, or powerpoint slides. We can shrink them down to about quarter of a page. Obviously not just bullet points to speak from. 3. Photo's are welcome. 4. We would not need source cross references 5. Title of presentation - Of course! Date, Job title of Author and Company represented. 6. An introductory summary of about 150 words would give the reader a flavour of what it's all about. 7. Style - we don't want out and out advertising but we do recognise that the author has a specialism in the product or process that will include some trade promotion. Sometimes it will be a unique process or equipment so trade specific must be allowed. 8. Date and any info relating to where or if this article may have been published before. 9. We can accept virtually any format. Word, Powerpoint, publisher, PDF or Open Office equivalents. 10. Also, to make it easy, the author can provide a word file to go along with his original powerpoint presentation and I/we can merge it together and select the required images. 11. A photo of author or collaborators. I really do look forward to receiving articles for publication. Richard Wood-Roe |