The Journal of
The  Institute of Circuit Technology
Vol 16 No 4
October 2023

Links to Contents 

10

Richard Wood-Roe
Journal Editor

In this issue of The Journal our first paper is an intriguing study of fine line etching of 16µm line pitch using software modelling to prepare the correct manufacturing parameters, with fabrication and assessment of the final product.

Our second paper explores the additive manufacturing of pcb's using laser assisted deposition of conductive and dielectric layers. 

Our final paper identifies the importance of the phosphorous content of the nickel layer when measuring the nickel thickness of an ENIG coating.

There is a review from Pete Starkey of the recent supplier webinars held in September. We have to report the passing of Harold Marshall, one of our industry characters. There is also the inclusion of industry and membership news.

I hope you find the contents of the Journal interesting. I welcome your feedback. This email address is being protected from spambots. You need JavaScript enabled to view it.

Bill Wilkie
Technical Director and Membership Secretary

           2023

            Details 

AUTUMN SEMINAR

We replaced the Autumn Seminar in September with a series of weekly webinars to allow our Industry Supply Chain to showcase existing products. This is a departure for the Institute, since we normally focus on technical matters. Two slots of 30 minutes each, between 4 and 5pm each Wednesday. We had to reschedule the last webinar to suit Peplertech, with Andrew Norton being ‘on-passage’, Portugal to The Canaries, in a small yacht!
September: Wednesday 6th at 4pm Neil Chamberlain, European Sales Manager of Polar Instruments and Leigh Allinson, Technical Sales Director of Ventec International.
September: Wednesday 13th Jim Francey, the RF Business Director of Isola and Gavin Barclay, Commercial Director of ACS Industries.
September: Wednesday 20th Mark Gordon, Managing Director of CCI Eurolam and Andre Bodegom, Managing Director of Adeon Technologies.
27th September: Andrew Norton, Managing Director of Peplertech – to be re-scheduled.

Attendance:
Neil Chamberlain - Polar Instruments
Happy Holden - PCB 007
Adam Wellington - Graphic
Dave Ward - Merlin Flex
Garth Allinson - Merlin Flex
Gary Byrne - Merlin Flex
John Smith - Graphic
Jonathan Sellers. A-Gas
Lawson Lightfoot - ICT
Martin Black - Merlin
MERLIN BOARDROOM - Merlin
Mark Gordon - CCI Eurolam
Paul Wells - Merlin PCB
Pete Starkey - ICT Recorder
Shaun Walker - Merlin Flex
GRAPHIC BOARDROOM - Graphic
Leigh Allinson - Ventec
Jim Francey - Isola
Gavin Barclay - ACS
Steve Thomas - Technic
Ben Wallen - Merlin pcb
Alun Morgan - EIPC
Himanshu Gajjar - Neuation Technologies
John Leafe - Teledyne UK
John Priday - Teledyne UK
Martin Goosey - ICT

Christmas Seminar
The Christmas Seminar is at the Majestic Hotel, Harrogate on 5th December with a Council Meeting and Fab group meeting to be followed by a technical seminar and sumptuous supper.

Sponsored by local companies: Faraday Circuits, Fineline VAR and GSPK Circuits.

Paper 1

Study on Wet Chemical Etching of Flexible Printed Circuit Board with 16‑μm Line Pitch
Yinggang Tang¹ · Hui Li² · Jiazheng Sheng² · Bin Sun³ · Jian Wang³ · Chupeng Zhang¹ · Daode Zhang¹ · Yicang Huang⁴ 

 
¹ School of Mechanical Engineering, Hubei University of Technology, Wuhan 430068, China. ² School of Power and Mechanical Engineering, Wuhan University, Wuhan 430072, China. ³ Jiangsu Leader-Tech Semiconductor Co., Ltd., Pizhou 221300, China. ⁴ R&D Center, Wuhan Second Ship Design and Research Institute, Wuhan 430205, China

Hui Li
Professor at Wuhan University,
China

As high-precision flexible printed circuit boards (FPCBs) are required in electronic products, it is necessary to study wet chemical etching to obtain precise FPCBs with a 16-μm line pitch. First, a π-shaped FPCB model with 16-μm line pitch is established using the finite element method. The evolution of the Cu etching profile and the concentration and velocity distribution of the CuCl₂ solution are then analyzed. To analyze the influence of conveyor speed and nozzle spray pressure on the Cu etching profile, wet chemical etching was tested along a horizontally conveyed line with CuCl₂ as the acid etchant. The resulting profiles were analyzed by scanning electron microscopy. The experimental results agreed well with the simulation results, and the Cu etching profile obviously depended on both the conveyor speed and nozzle spray pressure. In addition, increasing the conveyor speed under constant nozzle spray pressure (0.16 MPa or 0.17 MPa) decreased the etching depth and increased the etching factor. In particular, when the conveyor speed was set to 3.8 m/min and the nozzle spray pressure raised to 0.18 MPa, the fabricated FPCB had a line pitch of 16 μm, an etching depth of 7.55 μm, and an etching factor of 6.45. This method can aid the selection of parameters for the wet chemical etching process, enabling the future manufacture of high-precision FPCBs and complex FPCB circuits.

Keywords: FPCB · wet etching · finite element method · etching depth · etching factor

2.0 Introduction
Flexible printed circuit boards (FPCBs) are widely used in consumer electronic products owing to their light weight, small size, high wiring density, and small space limitations. ^1–5 Therefore, in-depth research on high-precision FPCB fabricating technology will promote the future development of the FPCB industry. High-precision FPCBs are fabricated by etching processes, which can be dry or wet. Dry etching, including ion milling,⁶ plasma etching,⁷ and reactive ion etching,⁸ achieves high dimensional control but requires complex and expensive equipment. In contrast, wet etching achieves high etching selectivity and a high etching rate using simple equipment with easy operations.^9–12 Therefore, wet etching can realize high-precision FPCBs. For example, the wet etching process has fabricated Cu with line pitches of 50 μm, 40 μm, and 30 μm.^13–15 To achieve consistently etched Cu interconnects with undercuts of less than 20 μm, the arrayed jet-stream etching technique was tweaked.¹⁶ With the increasing demand for precision electronic products, the fabrication of FPCB with 16 μm or finer line pitch has attracted much attention by wet etching. Some scholars have studied wet etching from the principle of the wet etching reaction of Cu to preliminary explorations of the wet chemical etching process.^17,18 Utilizing electroplating/ electroetching techniques, Mirvakili et al.¹⁹ micro-fabricated printed circuit boards with trace widths down to 3 μm. How- ever, the etching thickness is less easily controlled in electroplating/electroetching than in wet chemical etching. Gao et al. reduced the sample thickness by adopting the Cu/Ni co-assisted chemical etching method,²⁰ but chemical etching is prone to serious lateral etching. To improve this situation, a KOH solution was employed in two steps for etching to increase the aspect ratio.²¹ Wang et al. reduced the Cu-side etching from 25 μm to 5 μm²² using a multi-step etching process, which was overly complicated. This process has therefore been simplified and the process parameters optimized to reduce the lateral etching. The influences of bath temperature, conveyor speed, nozzle pressure, and bath specific gravity on etching efficiency have been studied during the etching process,²³ but it is costly. 

To lower the experimental cost, some researchers have numerically simulated the etching process. The common numerical methods included finite-difference time-domain simulations, the level set simulation method, and the finite element method. Time-domain simulations have revealed the influence of local surface curvature on the etch rate,^24,25
whereas the level set method has simulated wet anisotropic etching.^26,27 The wet chemical etching process has been simulated using the concentration fixed-grid method.^28,29 Among these techniques, the finite element method is the most suitable for studying the wet etching process, because it can solve the fluid velocity profiles and etchant concentration
distribution in cavities of arbitrary shapes.³⁰ In this study, based on the finite element method, a π-shaped FPCB etching model with 16-μm line pitch was established. The concentration and velocity distribution of
the CuCl₂ solution on both sides of the FPCB have been analyzed to study the evolution of the FPCB etching profile. Next, wet chemical etching has been tested and the FPCB etching profiles measured by scanning electron microscopy (SEM; MIRA3; Tescan, Brno, Czech Republic). Finally, the proper etching process parameters were determined. Based on the above results, an FPCB with 16-μm line pitch has been fabricated.

3.0 Wet Chemical Etching Simulation
The complex fabrication process of FPCB is demonstrated in two steps. The Section “Reaction Principle and Simulation Method” analyzes the etching reaction of FPCB and establishes an FPCB etching model with a 16-μm line pitch for the wet chemical etching simulation. The simulation results are presented in the Section “Simulation Results”.

4.0 Reaction Principle and Simulation Method
Understanding the basic etching reaction is essential for studying the wet chemical etching process of FPCB. The Cu on the etching surface reacts mainly with the CuCl₂ solution.

Fig. 1 Two-dimensional geometric model of FPCB
with 16-μm line pitch.

As the reaction proceeds, the Cu is dissolved and the CuCl₂ solution is consumed. The etching reaction is:¹⁷

(1)          Cu + CuCl₂ → 2CuCl

The etching process has been simulated using the finite element software COMSOL Multiphysics (COMSOL, Stockholm, Sweden). The Cu in the central region was taken as the research object. The two-dimensional geometric model of FPCB with 16-μm line pitch was established, as
shown in Fig. 1. The etching area is π-shaped. The photoresist is 2 μm thick and 10 μm wide, and the inlet and etching surface are 24 μm and 6 μm wide, respectively. The outlets at both sides are 2 μm thick.

Analyzing the etching simulation, the convection and diffusion of the CuCl2 solution were formed in the etching cavity. The mass flux of CuCl₂
is given by:³⁰

         (2)

where c denotes the CuCl₂ concentration, D is the reactant diffusivity, and u is the fluid velocity.

The initial concentration is the CuCl₂ concentration at the inlet. Taking the moving boundary of the model as the etching surface, the flux condition is expressed as:^{30
           (3)}
where k denotes the reaction rate constant at the etching surface, and n is the unit normal vector pointing outward from the computational domain.

To simulate the wet etching experiment, some parameter conditions must be set. Here, the CuCl₂ concentration was 0.45 mol/L*, the inlet velocity was 1 m/s, the diffusion coefficient was 7.27 × 10⁻¹⁰ m2/s,³⁰ the reaction rate constant was 6.19 × 10⁻⁶ m/s, and the anisotropic difference coefficient α was 0.2

Fig. 2 Mesh quality of two etching cavities.

To acquire accurate simulation results, the mesh division should be configured to a high mesh quality. Figure 2 shows the mesh quality of the etching cavity. The number of complete meshes was 7085 and the average and minimum unit masses were 0.85 and 0.17, respectively.

5.0 Simulation Results
Based on the model of the FPCB with 16-μm line pitch, the FPCB etching process was simulated under different conveyor speeds and nozzle spray pressures. The concentrations and velocity distributions of the etchant in the etching cavity were analyzed. For ease of understanding, the etching depth is defined as the vertical distance between the top of the remaining Cu at the center region and the bottom of the etching cavity. The etching factor is defined as the etching depth divided by the sum of the lateral etching widths on both sides of the FPCB surface. The profiles were extracted from the simulation results at three nozzle spray pressures and conveyor speeds, as shown in Fig. 3. The etching profiles are relatively smooth. The X and Y directions represent the lateral and depth etching
directions, respectively.

Fig. 3 Simulation results of etched profiles of FPCB under different conveyor speeds at nozzle spray pressure of
(a) 0.16 MPa, (b) 0.17 MPa, and (c) 0.18 MPa.

Table I shows the simulated etching depths and etching factors at the three nozzle spray pressures and conveyor speeds. As the conveyor speed increased from 3.8 m/min to 4.2 m/min under a nozzle spray pressure of 0.16 MPa, the etching depth decreased from 6.95 μm to 6.38 μm and the etching factor increased from 2.66 to 2.77. At 0.17 MPa and 0.18 MPa, the corresponding decreases in etching depth were 7.69–7.02 μm and 8.32–7.76 μm, respectively, and the corresponding increases in etching factors were 2.96–3.03 and 3.21–3.35, respectively. In addition, both the conveyor speed and nozzle spray pressure clearly influenced the Cu etching profile. The etching depths at the above-specified nozzle spray pressures and conveyor speeds varied by a maximum of 1.94 μm.

Table 1 Etching depth and etching factor under different conveyor speeds and nozzle spray pressures in the simulation.

To better understand the flow of etching solution in the etching cavity during etching, the concentrations and velocity distributions of the CuCl₂ solution in the etching cavity have been analyzed at the intermediate conditions (nozzle spray pressure = 0.17 MPa; conveyor speed = 4.0 m/min), as shown in Fig. 4. The central blank region presents the remaining Cu. The concentrations and velocity distributions of the solution on both sides of the etching cavities are almost symmetric because the solution was sprayed evenly at the inlet. As shown in Fig. 4a, the CuCl₂ concentration at the inlet was 0.45 mol/L. The etching process starts from the Cu exposed on the etching surface and the etching factor increased from 2.66 to 2.77. At 0.17 MPa and 0.18 MPa, the corresponding decreases in etching depth were 7.69–7.02 μm and 8.32–7.76 μm, respectively, and the corresponding increases in etching factors were 2.96–3.03 and 3.21–3.35, respectively. In addition, both the conveyor speed and nozzle spray pressure clearly influenced the Cu etching profile. The etching depths at the above-specified nozzle spray pressures and conveyor speeds varied by a maximum of 1.94 μm.
To better understand the flow of etching solution in the etching cavity during etching, the concentrations and velocity distributions of the CuCl₂ solution in the etching cavity have been analyzed at the intermediate conditions (nozzle spray pressure = 0.17 MPa; conveyor speed = 4.0 m/min), as shown in Fig. 4. The central blank region presents the remaining Cu. The concentrations and velocity distributions of the solution on both sides of the etching cavities are almost symmetric because the solution was sprayed evenly at the inlet.

Fig. 4 (a) Concentration and (b) velocity distribution of CuCl₂ solution in two etching cavities.

As shown in Fig. 4a, the CuCl₂ concentration at the inlet was 0.45 mol/L. The etching process starts from the Cu exposed on the etching surface and gradually proceeds toward the bottom. Both sides of the Cu are laterally etched by convection of the CuCl₂ solution. The lowest concentration (0.38 mol/L) appears at the bottom of the etching cavity. At this location, the low concentration might be explained by insufficient replenishment of the CuCl₂ solution after the reaction between CuCl₂ and Cu; specifically, the spent CuCl₂ solution cannot be replaced in time. As shown in Fig. 4b, the etching solution flows into the etching surface from the inlet and then flows from the outlets on both sides. The maximum and minimum veloci- ties are 2.25 m/s and 0 m/s at the outlets of both sides and the bottom of the etching cavity. The velocity distribution reveals an eddy current in the etching cavity caused by the convection circulation of the CuCl₂ solution and the natural diffusion of CuCl₂ on the etching surface.

6.0 Wet Chemical Etching Process
After the etching simulation, FPCB with 16-μm line pitch was fabricated using a wet chemical etching process. The FPCB profile was measured by SEM.

7.0 Fabrication of FPCB with 16‑μm Line Pitch
Figure 5a shows the fabrication process of the FPCB sample in a horizontally conveyed wet chemical etching line. The sample was first pre-cleaned with filtered water, then conveyed to the etching chamber for etching, where the CuCl₂ solution was sprayed evenly on the sample with the nozzle, as shown in Fig. 5b. Next, the sample was thoroughly cleaned in filtered water to remove the residual solution. Finally, the sample was air-dried prior to measurement.
During the wet chemical etching process, the conveyor speed and nozzle spray pressure were adjusted from 3.8 m/ min to 4.2 m/min and from 0.16 MPa to 0.18 MPa, respectively. The etching temperature and etching solution concentration were maintained constant at 35°C and 0.45 mol/L, respectively.

Fig. 5 (a) FPCB etching process and
(b) the nozzle device in the etching chamber.

8.0 Measurement of the FPCB Profile
Figure 6 shows SEM images of the etched FPCB profiles at the three conveyor speeds and nozzle spray pressures. The etching cavities on both sides were filled with glue to prevent cutting damage to the FPCB. The remaining Cu presents a trapezoidal shape (narrow top and wide bottom) in the center region, consistent with the simulation results in Fig. 4. The width ranges at the top and bottom were 3.90–5.17 μm and
6.24–8.65 μm, respectively. The change in the etching profile is reflected in the etching factor.

Fig. 6 SEM images of etched FPCB profiles under different conveyor speeds and nozzle spray pressures

The FPCB profiles (see Fig. 7) were extracted along the etched surfaces in Fig. 6. Table II displays the experimentally obtained etching depths and etching factors under the three nozzle spray pressures and conveyor speeds. As the conveyor speed increased from 3.8 m/min to 4.2 m/min, the etching factor increased from 3.77 to 5.27 and from 4.25 to 5.75 at nozzle spray pressures of 0.16 MPa and 0.17 MPa, respectively. However, under a nozzle spray pressure of 0.18 MPa, the etching factor decreased from 6.45 at 3.8 m/min to 4.65 at 4.2 m/ min. It was considered that the complicated wet chemical etching process was influenced by more factors than the two-dimensional etching simulation. In general, enlarging the etching factor deepened the etching profile and increased the verticality of the sidewalls.

 Fig. 7 Experimentally etched profiles of FPCB under different conveyor speeds at nozzle spray pressure of (a) 0.16 MPa, (b) 0.17 MPa, and (c)
0.18 MPa.

As additionally shown in Table 2, increasing the conveyor speed from 3.8 m/min to 4.2 m/min decreased the etching depth from 7.42 μm to 6.40 μm, from 7.50 μm to 6.50 μm, and from 7.55 μm to 6.61 μm at nozzle spray pressures of 0.16 MPa, 0.17 MPa, and 0.18 MPa, respectively. These etching depth trends are consistent with the simulation results in Fig. 3. In particular, at a conveyor speed of 3.8 m/min and a nozzle spray pressure of 0.18 MPa, an FPCB with of about 16-μm line pitch (the remaining Cu was 3.90 μm wide, the lateral etchings about the widths on both sides of the FPCB surface summed to 2.34 μm, and the bottom of the etching cavity was 9.45 μm wide in total) was successfully fabricated with an etching depth of 7.55 μm and an etching factor of 6.45.

Table 2 Etching depth and etching factor under different conveyor speeds and nozzle spray pressures in the experiment

9.0 Conclusions
Fabricating FPCBs with 16-μm line pitch has challenged the current electronic industry. In this work, the FPCB etching process was first modelled and simulated based on the finite element method. Next, FPCB samples with 16-μm line pitch were successfully fabricated using the wet etching process. The results of the finite element simulation agreed with the experiment results, demonstrating that both the conveyor speed and nozzle spray pressure clearly influence the Cu etching profile. In addition, increasing the conveyor speed decreases the etching depth and increases the etching factor at nozzle spray pressures of 0.16 MPa and 0.17 MPa. In particular, when the conveyor speed and nozzle spray pressure were set to 3.8 m/min and 0.18 MPa, respectively. an FPCB with 16-μm line pitch, an etching depth of 7.55 μm, and an etching factor of 6.45 was successfully fabricated.
This work will advance the future fabrication of complex FPCB circuits and the design of patterned circuits.

Acknowledgments This work was supported by the National Key R&D Program of China Grant Number No. 2019YFB1704600 and the Hubei Provincial Natural Science Foundation of China Grant Number No. 2020CFA032.

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Published with approval from the author © The Minerals, Metals & Materials Society 2023

Digital and Environmental Circuit Board Manufacturing Based on Continuous Laser Assisted Deposition

Michael Zenou, Ralph Birnbaum, Guy Nesher, Alex Stepinski

In the LIFT (Laser Induced Forward Transfer) technology, a material, evenly coated on a transparent carrier film, passes under a laser. The laser applies a short burst of energy to it. This releases perfectly consistent drops of material onto the substrate below. The material drops can then be sintered or cured inline, in the same machine. A great benefit is that this technology works for solder and polymers as well as for metals and ceramics. Multiple materials can be printed at the same time. This new technology opens the way to new advanced applications and the fabrication of innovative materials and novel applications. LIFT systems can work with many materials currently on the market and will also leave great freedom to innovate to both material engineers and chemists: they will be able to create products with significantly better properties than those achievable with current 3D printing technologies due to the low constraint requirement on the printed material. Viscosities can exceed 300,000 cPs and fillers of more than 40µm can be added. The current paper deals with one application of this technology, an innovative approach to manufacture circuit boards with the speed of printing.

Keywords: new equipment, materials printing, laser assisted deposition, advanced manufacturing, additive manufacturing.

1. Introduction

Additive Manufacturing has been around for roughly 3 decades. Even though it was the great hope for manufacturing, which today is roughly a trillion-dollar industry, additive manufacturing never really took a big share from the larger, manufacturing, industry. At roughly $21B, the additive manufacturing industry is just over 2% of all manufacturing and is used mainly as a prototyping tool.

The reason for this is the material challenge. Today’s additive manufacturing technologies are generally not able to print the certified, industrial grade materials used in manufacturing. This is especially true in the electronics industry. They are generally too viscous for existing 3D printers. In their place, close approximations are used^i,ii, sometimes with more expensive, proprietary materials, that look like the real thing, but lack in mechanical and especially electrical properties and functionalitiesⁱⁱⁱ. Some applications where an additive manufacturing solution using original materials would be useful but don’t exist today, are for coating materials, epoxy filling and gaskets and conductive bonding materials.

Ideally, the materials used for additive manufacturing would have to be the genuine certified industrial materials with all the desired characteristics in terms of temperature, viscosity, loading, etc. In electronics these would have to be printed at very high resolutions and accuracy. To make it economical, this would have to be done at high speed. And finally, since electronic components always consist of multiple materials, both organic and conductive, the solution must be able to handle multiple materials. 3D printing has made great progress in the past 3 decades, with huge advances in materials printing, but there is always some trade-off between these requirements.

Laser Induced Forward Transfer (LIFT), a technology first developed in 1968^iv and further developed ever since, can print materials with high viscosity, that hitherto, could not be printed. Materials with viscosities higher than 300,000 cPs can be printed. The technology has successfully been tested on silicone, ceramics, conductive epoxies, and metals^v. The resolution of the system currently goes down to 30um. In the same print, varying resolutions from 30um to 500um can be printed. Depending on the implementation, multiple different materials can be printed simultaneously, including polymers, metals and ceramics. This is all done at high speed, reaching 3 liters/hour, or 2,000 drops/second.

All along the electronics supply chain, there are areas where one material is being deposited, printed, etched… onto another. This is true for PCB, SMT assembly, semiconductor packaging, as well as for EMS.
Some applications include:
- Printing the conductive traces and filling the vias
- Solder Mask, using the original solder resist inks.
- Solder paste deposition
- Conformal coating
Further down the electronics supply chain, with LIFT you can print small Faraday cages and gaskets using hitherto unprintable materials, such as silicon, opening the way for new designs in electronics

2. The Technology
In LIFT, or Laser Induced Forward Transfer, a viscous material is deposited on the underside of a transparent foil. The material is squeezed between two cylindrical rolls to get a uniform layer. The material is then carried below the laser, which hits the material with a nano-punch, creating a tiny vapor bubble, which causes one drop of material to be released on to the substrate at the desired location and resolution.

Fig 1: Continuous Laser Assisted Deposition

The technology is contact-less, and does not make any use of masks, stencils or cloggable nozzles. Materials with very high viscosity, over 300,000 cPs can be printed.

All post-processing is inline. Both UV and thermal curing is completed in the same station, thereby saving both time and space. Laser sintering and ablation are also performed

Compared to existing technologies, such as screen printing, or jet dispensers, LIFT offers great benefits. Traditional digital technologies are defined by the nozzle size, which limits viscosity, speed and resolution. Traditional non-digital technologies are defined by the mesh size, which limits the layer thickness and resolution. Laser Induced Forward Transfer technology has neither nozzle, nor mesh, giving it full flexibility.

It has all the digital flexibility of jet dispensers, with the ability to print multiple materials on multiple layers. With throughputs comparable (but not quite equal to) screen printers. Resolutions are greater than either jet dispensers or screen printers. No nozzles to clean, and no stencils to maintain, reduces the maintenance costs of LIFT technology

To summarize:
- LIFT technology produces commercial ready functional objects, not prototypes
- The functional properties of the 3D printed object are the same as the original, having been printed with the same certified materials
- Just like other 3D printing technologies, LIFT technology gives the designer full flexibility in terms of design
- Multiple different materials can be printed in one object
- Contactless, mask-less, and nozzle-free, make for a lower cost of ownership
- The inclusion of post-processing, in terms of curing, sintering and ablation, makes for a faster and simpler production process

3. Applications
Anywhere along the electronics supply chain where one material is deposited onto another, LIFT can be applied. Conductive traces can be printed made of different commercial metallic paste (silver, copper, carbon,) like shown in Figure 2. The copper paste is commercially available^vi, as well as the solder resist.. No other system is capable of printing copper and solder mask together, reducing the number of process steps. It also reduces the environmental impact considerably.

Figure 2: single layer PCB showing both copper metallization
and solder mask coating

Different type of coating can be printed like solder mask, waterproof, glob top, and others. Adhesives of all types can be printed, such as solder paste, conductive epoxy, two component epoxies, and others.

Fig 3: Complex conductive layer geometry from Gerber file.
Material is CoPPrint

There are additional applications in the SMT world. Solder paste is a prime candidate for this technology, and several different standard solder pastes have been successfully printed. Resolutions of solder paste balls go down to 100µm solder ball diameter for Type 6 solder paste. Being a digital technology, both large and small components can be printed in the same print, even printing on other components, for multiple chip stacks. As a comparison, some of the fastest jet dispensers reach on the order of 100,000 solder balls/hour. This technology can go over 7,000,000 solder balls/hour.

Die bonding is an application that has been shown to have benefits with this approach too. A variety of adhesive pastes have been tested, with high flatness uniformity. Throughputs can be higher than 10,000 droplets/sec. A wide range of other adhesives can be printed with resolutions down to 50um, including unusual shapes with sharp corners and curved sides are not a challenge. Throughputs over 300mm/sec and high accuracy, below 5um. Multiple adhesives can be printed together

LIFT offers a fabless solution to inner-layer PCB manufacturing. The new process will print inner layers digitally, substantially speeding up inner layer process, for multi-layer boards and HDI layers. The process delivers metallization and dielectrics in an additive manufacturing way. Multiple layers can be printed, printing the filled vias as the process builds up. The outer layers are then finished with traditional processes. If desired, the solder mask, pad finish and legend using industrial grade materials can also be printed with the same LIFT process.

Fig 4: 3-D representation of features.

4. The Multilayer Process

The new hybrid process involves building up the inner layers, one layer at a time. The dielectric layers are laid down together with the via interconnects, followed by the conductive circuity on top. The feature sizes the LIFT process can currently support are shown in Table 1.

Table 1: Feature sizes for hybrid PCB process using C.L.A.D

A copper trace can be deposited with a width of 50µm. The system laser can then be used to ablate the copper, trimming it down to 30µm. Vias size down to 60 µm can be filled with copper.

Figure 5: Print timings of 250mmX250mm PCB layers

Print timings of a PCB layer are shown in Figure 5. Printing the metal traces, dielectric layer, and via interconnects, can be done in roughly 15 minutes. No drilling is required, since the via interconnect is printed on the fly, together with the dielectric layer. More via interconnects won’t increase the timing. There is no additional cost to complexity with additive manufacturing.

The hybrid approach to printing a multi-layer HDI board with LIFT technology starts with a plain copper sheet that is used by the industry today, the copper sheet could be a plain sheet or a metal coated sheet. For example, copper coated with a thin film of copper on top or other metal in any thickness.

A dielectric layer and the metal layer are deposited on top of the copper sheet in very high resolution one layer after the other. The LIFT technology allows any number of materials, so both dielectric and copper can be printed at the same time in any sequence that will support the final properties. It is also possible to add post-processing during the printing sessions when needed and ablate excess of material or sinter the metal traces where necessary. The same laser for the LIFT process can be used for laser ablation, and for sintering the copper. A UV lamp can be added for the dielectric polymerization as well as a thermal source for drying.

If a copper trace is required smaller than the deposition limits, it can be ablated down to 30µm, leaving no residue on the dielectric.

The manufacturing of the next layer will be identical, only instead of copper traces, the via interconnects are printed simultaneously with the dielectric. The microvias are built up as the layers are built up, so there is no drilling involved. This process is repeated for as many layers as required:
- Copper and dielectric deposition
- Post processing
- Microvia interconnect and dielectric deposition
- Rinse, repeat

After the final inner layer is laid down, an additional copper film is used as a top layer. This is then placed in a thermal press to shrink and bind. The two outer copper layers can then be removed, leaving a sandwich of two thin copper films, with multiple HDI layers in between.

The two outer layers are then printed using a standard photo-lithography process. The board can then be brought back to the LIFT station for solder mask deposition.

To summarize:
1) Start with a thin copper film
2) Deposit both dielectric material and copper traces
3) Post process with laser, and UV or thermal sources
4) Repeat for additional inner layers
5) Top with thin copper film
6) Hot press
7) Remove outer copper layers
8) Outer layer photolithography
9) Solder mask

This process combines the benefits of the LIFT technology without the need to recertify the inner layers with the final customer.

5. Summary and benefits

The benefits of the LIFT technology are:

• The technology supports multi-material deposition: Conductors, dielectrics and solder mask
• It’s an additive process: No imaging, developing or etching. Clean and integrated process, with less material wastage
• High production speeds: 15 minutes per PCB layer (250mmX250mm)
• Supports complex designs: 30μm to 500μm dynamic resolution
• Supports dynamic height: Flexible aspect ratios, straight walls, no undercut
• High repeatability: Uniform layer height
• Non-contact: non-planar substrate capabilities, no nozzles to clog or masks to clean
• Digital process: Full customization and freedom of design
• Flexible laser technology: No special proprietary inks required

This technology can give a substantial boost to a high-mix, low-volume shop. There are no overhead costs, such as would be with screen printing technologies, and as there is no cost to complexity, designs that are currently produced in weeks, can be done in an hour. Since the outer layers are not touched, the customer usually doesn’t interfere with the production process. This will speed up the manufacturing process, while reducing costs. The technology could prove to be a big boost to on-shoring PCB production in the near future.

ⁱ M. Zarek, M. Layani, I. Cooperstein, E. Sachyani, D. Cohn, S. Magdassi, Adv. Mater. 2016, 28, 4449.
ⁱⁱ S.-Y. Wu, C. Yang, W. Hsu, L. Lin, Microsyst. Nanoeng. 2015, 1, 15013.
ⁱⁱⁱ Y. Yamamoto, S. Harada, D. Yamamoto, W. Honda, T. Arie, S. Akita, K. Takei, Sci. Adv. 2016, 2, e1601473.
^iv Brisbane, A.D. Method for Vapour Depositing a Material in the Form of a Pattern. Great. Britain Patent GB1,138,084, 27 December 1968.
^v M. Zenou, A. Sa’ar, Z. Kotler, Laser jetting of femto-liter metal droplets for high resolution 3D printed structures, Scientific Reports, 10.1038/srep17265, 5, 1, (2015).
^vi https://www.copprint.com/

Understanding Electroless Nickel Thickness in ENIG and ENEPIG
Robert Weber, Fischer Technology, Inc.

Robert Weber
Technical Director
Fischer Technology, Inc.

Abstract
IPC-4552 and IPC-4556 are industry performance specifications for ENIG (Electroless Nickel/Immersion Gold) and ENEPIG (Electroless Nickel/Electroless Palladium/Immersion Gold) as used for the surface finishes for printed wiring boards (PWBs). As both surface finishes are considered multifunctional in nature—solderable, wire bondable, and usable for contact switches—these performance specifications detail the many considerations for these critical surface finishes. One area of detail surrounds the acceptable coating thicknesses of the different layers of both PWB surface finishes. Much of the attention paid to ENIG and ENEPIG is focused on the precious metal layers: gold for ENIG and both gold and palladium for ENEPIG. Both documents also specify the thickness requirements for the electroless nickel layer; however, these requirements are often misunderstood. The thickness and phosphorus content of the
electroless nickel layer play critical roles in the solderability, functionality, and reliability of modern electronics. Thickness measurements of electroless nickel are affected by the phosphorus content (wt.% P) in the nickel deposit. Therefore, the phosphorus content (wt.% P) in the deposit must be considered a critical variable when creating an uncertainty budget and measuring the thickness of electroless nickel.

Introduction
While the current focus in the electronics industry is chips, components, and microelectronics, the PWB also plays a vital role. Continued miniaturization and environmental considerations, such Restriction of Hazardous Substances Directives (RoHS), have led the industry to create and improve surface finishes to meet the demands of current and future generation electronic assemblies. Two PWB finishes have become very common: ENIG and ENEPIG. The industry trade association, IPC, released specification IPC-4552 in 2002^[1] to help standardize the global printed circuit board (PWB) industry around a specification for ENIG. Specification IPC-4556 was released in 2013^[2] to establish industry standards around ENEPIG surface finishes.

The electroless nickel layer plays important roles in the functionality of printed boards. Electroless nickel provides a diffusion barrier between the copper basis metal and the surface finish layers of immersion gold (ENIG) or electroless palladium and gold (ENEPIG). It also provides a stable metallization for wire bonding and acts as a wear-resistant layer for switch-pad applications that copper or other copper-basis surface finishes cannot offer. The formation of nickel tin (Ni3Sn4) intermetallic compounds (IMCs) have been shown to offer similar long-term reliability when compared to the copper tin IMCs (Cu6Sn5 and Cu3Sn) that have been the standard for reliability studies since the inception of the electronics industry^[3]. Both IPC-4552B and IPC-4556 specify the electroless nickel thickness for rigid boards shall be 3–6 μm [118.1–236.2 μin]^{[4, 5]}. IPC-4556 contains an additional requirement to apply a ± 4 sigma (four standard deviations) from the mean to account for measurement uncertainty. (Note that IPC-4552 also provides electroless nickel thickness requirements for flex printed circuit boards. For brevity, this paper addresses only rigid boards, although the concepts detailed can be applied to flex boards.)

The background for thickness range requirements for electroless nickel arise from both practical and physical requirements. IPC-4552B indicates electroless nickel thicknesses below 3 μm may be appropriate for high frequency applications^[6]. However, electroless nickel thicknesses below 1.27 μm [50 μin] are not recommended due to increased potential for copper diffusion through the electroless nickel layer^[7]. Practically, the time to deposit 1.27 μm of electroless nickel is shorter than the time to deposit the required thicknesses of immersion gold, especially important on an automated plating line. Plating the minimum 1.27 μm would require freshly deposited nickel PWBs to be placed into a “holding station” or rinse water tank for an extended period. This risks passivation of the nickel prior to the immersion gold (or palladium) deposit. Passivated nickel presents problems with the adhesion and solderability of subsequent plating layers. To minimize hold times and potential impact on the nickel, the minimum thickness established at 3 μm. This was found to work well with automated plating lines, as well as providing an excellent minimum thickness for wire bonding. The maximum thickness of 6 μm [236.2 μin] was incorporated to prevent high insertion forces and, therefore, possible damage for press fit pins into PWB through holes^[8].

 X-ray fluorescence (XRF) instrumentation is the only accepted IPC-4552B metrology method^[9] to measure thicknesses for plated layers. IPC-4556 does not restrict ENEPIG thickness measurements to XRF but Appendices 4 and 9 highlight and detail specific guidance and considerations for use of XRF to measure ENEPIG^[10]. XRF instruments calculate thicknesses by determining the amount of mass of material present in a defined measurement area. The analysis, or measurement, area of a specific XRF measurement is colloquially known as the “spot size.” The spot size is defined by type of XRF system used, either with mechanical collimators or polycapillary optics. IPC-4552B specifies the use of either a 0.3 mm or 0.6 mm mechanical collimator, or using a system equipped with polycapillary optics (measurements made with polycapillary optics shall be made with a scan over the surface)^[11]. IPC-4556 does not directly specify a spot size, but does state that measurement spot size “shall not exceed 30% of the
feature size being measured”^[12].

Calculation of coating thickness using XRF, while complicated, can be simplified to a core principle: measuring the amount of mass of material within a known measurement surface area. The measurement surface area is defined by either the collimator size or polycapillary optic spot size. An XRF instrument observes and quantifies an amount of mass of material, uses known or user input for the density of the material, and calculates a thickness value.

Thus, calculating the thickness of electroless nickel thicknesses presents challenges. Electroless nickel is a self-sustaining, autocatalytic reduction process using hypophosphite chemistry^[13]. As the nickel deposits on a substrate, by design, a quantity of phosphorus is incorporated within the nickel layer. The addition of phosphorus changes the density of the deposit. As described in the paragraph above, XRF measurements use mass in a defined surface area to derive a layer thickness. Changes in density, if not included in the measurement calculation, will present themselves as a change in layer thickness.

Accurate measurement of the electroless nickel layer thickness is possible if a user corrects for density changes caused by the inclusion of phosphorus in the nickel deposit in a specific sample. The thickness measurement can be calculated with the appropriate density (e.g., fixed percentage; 92% Ni, 8% P) of the specific sample. Some XRF instruments are capable of directly measuring the phosphorus content (calculating the alloy percentage in wt.%) in each sample and will automatically calculate a thickness with the correct density.

Experiment
Testing for the effects of phosphorus content on thickness was conducted on a ENIG calibration standard, serial identifier AVPQ (Table 1). The sample was measured using a calibrated XRF instrument with collimated optics and measured with the test conditions as detailed in Table 2.

The sample was measured five (5) times under repeatability conditions^[14] (same person, same location, short time frame, same instrument, etc.). The phosphorus content was initially set at 5%; the measurement calculation recipe was then manually adjusted (Figure 1) between each group of measurements, in increments of 1%, to a final value of 13 wt.% P. Mean values and standard deviations were calculated from the individual measurements (Table 3). The calculated thickness was plotted vs. the wt.% P used in the measurement calculation (Figure 2).

Fig 1: Setting the Phosphorous Percentage in the Measurement Recipe

Additional testing was performed on a second sample to evaluate how different percentages of phosphorus affected electroless nickel thickness measurements near the lower limit of the IPC specifications. Testing was performed using a certified electroless nickel sample at 3.05 μm [120.1 μin] containing 8% phosphorus over a solid copper base. The phosphorus content for the thickness calculation was manually varied, in the measurement settings (Figure 1), from 5 – 10 wt.% P. This data is displayed in Table 4.

Discussion
The effects of phosphorus content on electroless nickel are apparent from the data shown in Tables 3 and 4 and graphically represented in Figure 2. The data clearly show the effects changing phosphorus content has on the layer thickness of an electroless nickel deposit. This explains why the actual phosphorus content in the deposit must be considered by both PWB manufacturers and end users when evaluating electroless nickel thickness versus the IPC specifications. These considerations become more relevant when part acceptance and rejection are considered for out-of specification thicknesses for electroless nickel.

The risk of rejecting good parts, or conversely accepting failing parts, is real if we accept or reject solely on the thickness of the electroless nickel layer. Recall from Figure 2 and Table 3, the dimensional thickness of the electroless nickel layer is affected by phosphorus content in the layer. From Table 4, we see how an understanding of these effects is critical when the sample is at, or near, the specification’s tolerance (Figure 3, Figure 4). Referring to Table 4, the sample, as measured at 8% phosphorus, will pass both IPC-4552B and IPC-4556 minimum electroless nickel thickness but will fail if the sample is measured at 7% phosphorus.

The potential for false rejection or acceptance increases when we look at ENEPIG and IPC-4556. As mentioned earlier from Figure 4, with ENEPIG, the standard deviation of the electroless nickel measurements must also be considered. Figure 5 shows a plot of 300 randomly generated data points. In this case, using the measurement standard deviation (1σ) of 0.005 μm from Table 4, the part must measure a minimum of 3.02 μm to meet a minimum thickness of 3 μm ± 4σ.

Conclusion
Both IPC-4552 and IPC-4556 are important industry standards for the manufacturing of reliable electronic assemblies. Much of the attention in printed wiring boards is paid to the precious metals. The electroless nickel layer is also important—for reasons of solderability, shelf life, durability, and dimensional requirements for press fit pins.

Both IPC specifications apply a 3–6 μm [118.1–236.2 μin] thickness specification to the electroless nickel layer. This creates potential problems for both the PWB manufacturer and the end user; there may be false rejections or acceptance because an incorrect phosphorus content was used to calculate the thickness. This potential thickness measurement error is most relevant for parts with electroless nickel thickness at, or very close to, the minimum or maximum tolerances.

Care should be taken to use the correct phosphorus content for the sample being measured or use XRF instrumentation capable of directly evaluating the wt.% P in the sample being measured. 

References
^[1] Specification for Electroless Nickel/Immersion Gold (ENIG) Plating for Printed Boards, IPC-4552B. (2021). IPC International, Inc., Bannockburn, Illinois, USA.
^[2] Specification for Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG) for Plating Printed Circuit Boards, IPC-4556. (2013). IPC International, Inc., Bannockburn, Illinois, USA.
^[3] Lee, C. C.. P. J. Wang. and J. S. Kim. (2007). Are Intermetallics in Solder Joints Really Brittle? 2007 Proceedings 57th Electronic Components and Technology Conference, pp. 648-652, doi: 10.1109/ECTC.2007.373866.
^[4] Specification for Electroless Nickel/Immersion Gold (ENIG) Plating for Printed Boards, IPC-4552B. (2021). p. 6, IPC International, Inc., Bannockburn, Illinois, USA.
^[5] Specification for Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG) for Plating Printed Circuit Boards, IPC-4556. (2013). p. 4, IPC International, Inc., Bannockburn, Illinois, USA.
^[6] Specification for Electroless Nickel/Immersion Gold (ENIG) Plating for Printed Boards, IPC-4552B. (2021). p. 23, IPC International, Inc., Bannockburn, Illinois, USA.
^[7] Specification for Electroless Nickel/Immersion Gold (ENIG) Plating for Printed Boards, IPC-4552B. (2021). p. 23, IPC International, Inc., Bannockburn, Illinois, USA.
^[8] O’Brien, Gerard, ST&S Group. Interview Conducted by Robert Weber, 15 Sep. 2022.
^[9] Specification for Electroless Nickel/Immersion Gold (ENIG) Plating for Printed Boards, IPC-4552B.
(2021). p. 7. IPC International, Inc., Bannockburn, Illinois, USA.
^[10] Specification for Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG) for Plating Printed Circuit Boards, IPC-4556. (2013). p. 4, IPC International, Inc., Bannockburn, Illinois, USA. 
^[11] Specification for Electroless Nickel/Immersion Gold (ENIG) Plating for Printed Boards, IPC-4552B. (2021). p. 12, IPC International, Inc., Bannockburn, Illinois, USA.
^[12] Specification for Electroless Nickel/Immersion Gold (ENIG) Plating for Printed Boards, IPC-4552B. (2021). p. 8, IPC International, Inc., Bannockburn, Illinois, USA.
^[12] Specification for Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG) for Plating Printed Circuit Boards, IPC-4556. (2013). IPC International, Inc., Bannockburn, Illinois, USA.
^[13] Specification for Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG) for Plating Printed Circuit Boards, IPC-4556. (2013). p. 12, IPC International, Inc., Bannockburn, Illinois, USA.
^[14] ISO 5725-1:1994 Accuracy (trueness and precision) of measurement methods and results – Part 1: General principles and definitions, International Organization for Standardization, Geneva, Switzerland.
^[15] Specification for Electroless Nickel/Immersion Gold (ENIG) Plating for Printed Boards, IPC-4552B. (2021). p. 6. IPC International, Inc., Bannockburn, Illinois, USA.
^[16] Specification for Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG) for Plating Printed Circuit Boards, IPC-4556. (2013). p. 4, IPC International, Inc., Bannockburn, Illinois, USA.

1.0 Introduction
In response to a suggestion from Neil Martin, Chairman of Merlin PCB Group, ICT Technical Director Bill Wilkie organised a series of Institute of Circuit Technology Supply-Chain Webinars designed to let corporate supplier-members present their technical specialities and showcase their products. The 4pm slot each Wednesday afternoon in September gave a valuable opportunity to extend our knowledge and benefit from an informative hour of live presentations.

Neil Chamberlain
Polar Instruments

 Leigh Allinson
Ventec International Group

Jim Francey
Isola 

Andre Bodegom
Adeon Technologies

Mark Gordon
CCI Eurolam

7.0 CCI Eurolam group

Based in France, CCI Eurolam have been supplying the electronics manufacturing industry for 55 years, the original company having been founded over 100 years ago and still family-owned. The group had expertise in a wide array of electronics manufacturing technologies, covering the PCB fabrication and assembly industries, through ceramic circuits and printed electronics to semiconductors. It was active through a complex electronics ecosystem in the EMEA area, with business units in Germany, UK, Spain and Netherlands. Mark Gordon, Managing Director of the UK operation, explained that the group had 150 employees, including 35 sales engineers and 17 applications engineers, and the ability to communicate in 14 spoken languages.
Gordon presented an overview of the group’s extensive product range which included PCB substrates, electronics grade foils, surface treatments and finishes, laminating and drilling materials and imaging materials.
For the PCB fabricator, CCI Eurolam supplied rigid laminates and prepregs from EMC and Kingboard. Gordon mentioned that EMC could provide a mass-lam service, including polyimide if required. High-reliability substrates came from Arlon, flexible laminates from DuPont, RF and microwave substrates from Rogers, copper foils from UCF, Furukawa and Kingboard. Besides all of these substrate materials, CCI Eurolam provided a range of drill entry and backing boards from Alltech and LCOA, drills and routers from TCT, release films, press pads and conformals from Pacothane, dry film photoresist from DuPont, PCB inkjet materials from Agfa, and contact-cleaning processes from KSM-Superclean.
This comprehensive products list, together with the specialist software and equipment offered by Adeon, represented a true one-stop-shop for PCB manufacture: everything readily available and backed by specialist applications and service support and full laboratory facilities.
As well as PCBs, a division of CCI Eurolam was a major supplier to printed electronics and thick film manufacturers, again with a comprehensive range of substrates, inks and pastes. Another company within the group was distributor of soldering products for the electronics manufacturing industry.
So what made CCI Eurolam special? What was the goal? What was the mission? In Gordon’s words it was to make the supply chain stronger throughout Europe, the Middle East and Africa, by stocking products locally, with the facility to cut and tool materials to the customer’s requirement and with full traceability.

This was a very successful format and went down well with the attendees and presenters:

Harold Marshall 9th August 1940 - 26th August 2023

We are sorry to have to announce the passing of Industry stalwart Harold Marshall. Born in Bolton, Harold attended Sunning Hill primary school and Bolton County Grammar, founding Vantage Circuit Products Ltd in 1987. Harold was an electro-chemist and worked initially in the laboratory at the former De Havilland aircraft works in Lostock and held senior positions in Imasa Silvercrown before branching out on his own with Chemlec Solutions and latterly with Vantage Circuit Products in Farnworth. He also spent time at TDS during their hay day in the 1980’s. Harold was a very gregarious individual, who always attended the many industry events and was sure to be found on his feet asking questions and thanking speakers. He was a very determined character, who threw himself into every venture, always ready to prove a point or have a jest. He was good company, enjoying his London club and the frequent outings as the pcb Industry expanded.
The funeral was held on the 7th September 2023 at Bolton.
With Thanks to the people who knew him:
Terry Thorpe, Tom Goodall, Alan Beddow, John Dutton, Darryl Birchall, Brian Richards, David Ormerod,  Peter Lymm, Phil Ward, Sandy Bryce, Martin Bunce, David Woodley, Ken Dobson, Steve Law, Keith Rickhuss, Ian Mayoh, Stuart McDonald, Terry Boby, Richard Houghton, Rex Rozario, Steve Jones, Richard Wood-Roe.

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Section 8

Industry News

Many customers have asked for readings of insertion loss at specific frequencies to be added in the Si9000e user interface in order to facilitate specifying Delta-L or SPP or other loss method testing. The latest Si9000e does just that – the insertion loss results at user nominated frequencies are now displayed alongside the All Losses plot.

For details, along with all the other recent enhancements please follow this link to this presentation. Read More »

Section 9

Membership News 

Bill Wilkie
Technical Director and Membership Secretary, ICT.

New Members

Section 11

ICT Council Members

Council Members

Emma Hudson (Chair), Andy Cobley (Past Chairman), Steve Payne (Hon Deputy Chairman), Chris Wall (Treasurer), William Wilkie (Technical Director, Hon Sec, Membership & Events), Richard Wood-Roe (Journal Editor & Web Site),  Jim Francey, Martin Goosey, Lynn Houghton, Pete Starkey, Francesca Stern and Bob Willis, 

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Section 12

Editors Notes

The ICT Journal

Richard Wood-Roe
Journal Editor

Instructions / Hints for Contributors

1. As it is a digital format the length is not an issue. Short is better than none at all!

2. Article can be a paper or a text version of a seminar or company presentation. Please include data tables, graphs, or powerpoint slides. We can shrink them down to about quarter of a page. Obviously not just bullet points to speak from.

3. Photo's are welcome.

4. We would not need  source cross references

5. Title of presentation - Of course! Date, Job title of Author and Company represented.

6. An introductory summary of about 150 words would give the reader a flavour of what it's all about.

7. Style - we don't want out and out advertising but we do recognise that the author has a specialism in the product or process that will include some trade promotion. Sometimes it will be a unique process or equipment so trade specific must be allowed.

8. Date and any info relating to where or if this article may have been published before.

9. We can accept virtually any format. Word, Powerpoint, publisher, PDF or Open Office equivalents. 

10. Also, to make it easy, the author can provide a word file to go along with his original powerpoint presentation and I/we can merge it together and select the required images. 

11. A photo of author or collaborators.

I really do look forward to receiving articles for publication.

Richard Wood-Roe

This email address is being protected from spambots. You need JavaScript enabled to view it.

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