ict logo The Journal of

The  Institute of Circuit Technology

Vol 15 No 1

March 2022

Links to Contents  

  Author  Section


Steve Payne  1

Calendar of Events

Bill Wilkie  2

Paper 1: The Power Mesh Architecture for PCB's

Happy Holden  3

Paper 2: Microvia Process Guidelines

Stan Heltzel 4

AGM and Technical Seminar March 30th 2022 

Pete Starkey  5
Technical Seminar November 30th 2021  Pete Starkey 6

Director's Report

 Bill Wilkie 


Industry News:  Parachem, Atotech, CCI Eurolam, Eurotech, Merlin Circuit Technology, Teledyne Labtech, Ventec and Zot


Membership Update:  New Members and Grading


Corporate Members


Council Members


Editors Notes

Lynn Houghton



Section 1



steve payne

Steve Payne,
Project Manager,
iNEMI and 
Vice Chair ICT


Steve Payne

The Editorial for this issue cannot ignore recent events as we start to emerge from the pandemic, another tragedy is occurring in Ukraine with just as serious consequences. Our thoughts are very much with the victims directly and indirectly affected by these terrible events.

On a more salutary note, at the ICT Council meeting of 21st February I was graded as an Honorary Fellow of the Institute of Circuit Technology, “in recognition of my service to the Institute”. I’m truly honoured and very appreciative of this recognition and it inspired me to look back at my time in our industry, (very briefly you’ll be glad to know!)

I fell into our industry almost by accident in that I was offered a job by GEC Marconi, and in Chelmsford at that time there were many 1000s of employees spread over very many sites such that Marconi had their own bus service. Taking the Marconi bus on the first morning I duly got off at the wrong site and ended up at a PCB production facility known as the MAT Lab, (MAT stood for Microcircuits Assembly Techniques), this was at Marconi Research Laboratories in Great Baddow. There I worked with some great colleagues, many of whom have become very good friends and have made their own significant contribution to our industry.

I joined the Institute several years after joining Marconi; it was on 12th October 1979 I joined as an Associate member (#583), becoming a full member on 22nd June 1985 and a Fellow on 24th October 1997. I joined the ICT Council on 20th January 1998 and first became Chairman on 15th February 2000 serving to August 2001. I served as Chairman again between February 2007 until 2010; I currently serve as Vice-Chair. I was also a member of the old PCIF Management Board (Richard Wood-Roe was then Chairman), not sure of my starting date but there until the merger with the FEI. I’m particularly glad to have played a small role in “kicking off” the PCB Fabricators Group, which I Chaired for the first 18 months.

The Institute has changed, as has our industry in a considerable way. When first becoming Chairman, the ICT had less than 150 members and probably significantly less in real terms as the membership list was woefully outdated. The pivotal change came with the appointment of Bill Wilkie, and it is no exaggeration to say we’ve not looked back since.

Looking forward, the ICT has a very important role to play. By providing focused educational courses on PCB technology, through the Annual Foundation Course and dissemination of applied research and development through the regular online and face-to-face Evening Symposiums and Annual Conference. The PCB Fabricators group is a unique platform for this section of the PCB supply chain to have a unified voice, so important in this seemingly volatile business environment. If I have one hope and request it is for a younger element to step forward and participate in the ICT: its events, quarterly journal and maybe a few to also consider a future role on the ICT Council.

Steve Payne
Vice Chair ICT

Go back to Contents


Section 2 Calendar of Events 

bill wilkie

Bill Wilkie
Technical Director and Membership Secretary, Institute of Circuit Technology


June 8th

April 11th - 14th

March 22nd


November 30th

September 7th

1st June

6th April - 27th May

25th February



Annual Symposium - Read more....

Annual Foundation Course - Read more....

AGM and Webinar Meeting


Autumn Seminar at Meriden

Autumn Webinar 

Annual Symposium Webinar

Foundation Course Webinar Lectures

AGM and Webinar Meeting

 Go back to Contents


Section 3

A Design Technology Innovation

The Power Mesh Architecture for PCBs

Happy Holden


 happy holden

Happy Holden



A significant decrease in HDI substrate production cost can be achieved by reducing the number of substrate layers from conventional through-hole multilayers and microvia multilayers of eight, ten, twelve and more to four. Besides reducing direct processing steps, yield will increase as defect producing operations are eliminated.

In the mid 1990’s, thin film multichip modules (MCM-D) were going to be the salvation for the interconnect industry. The fine-line lithography was going to allow miniaturization with ease. Unfortunately, the four or five metal layers to which integrated circuits were wire bonded proved to be too expensive when compared to printed circuits multilayers and the emerging silicon integration on ball grid arrays.

The Interconnected Mesh Power System (IMPS) topology was created to reduce the cost and metal layers on thin-film and ceramic multichip modules. The IMPS topology can reduce the metal layers to only two or three. This results in a substantial cost reduction and simplification while not affecting electrical performance.

Power Mesh Architecture is the result of applying IMPS lessons to the common microvia multilayer. A four-layer structure is used for the printed circuit. This reduced layer count microvia multilayer is so efficient in layout, it can replace three times (3X) the number of normal signal inner-layers on a conventional through-hole multilayer and the power and ground planes they require.

II. Background - IMPS
The scientists at the High-Density Electronics Center (HiDEC) of the University of Arkansas, Fayettville, AR. invented IMPS in the mid 1990’s[1]. IMPS allows a low inductance planar power and ground distribution, as well as dense, controlled-impedance, low crosstalk signal transmission in only two wiring layers. Figure 1 shows the basic IMPS topology.

The conventional metal wiring topology is to have signals on one-metal layer and power and ground on separate metal- layers. The resulting usage of these expensive metals layers is quite low. Signal layers may have only 50% to 60 % utilization and power / ground layers only half that amount. The explanation is quite simple, while the metal conductors

may be made smaller (if signal losses can be tolerated), the spacing cannot. High- speed, fast-risetime signals are sensitive to crosstalk, so the signals still must be separated. IMPS uses that separation to route power and ground. To prevent current starvation at devices, an adjacent metal layer running orthogonal is connected by buried vias at each junction were the two layers cross each other. This layer-pair topology is an “interconnected mesh” can thus provide all the power / ground connections without voltage loss and connect the signal for these devices.

Picture1bFigure 1. Interconnected Mesh Power System (IMPS) is a new and very cost-effective structure.

Picture2aFigure 2a. Electrical performance of IMPS is very close to solid planes. A. Power distribution impedance versus frequency using HP8510 network analyzer. Picture2bFigure 2b.  Power distribution impedance using the HP4291A impedance meter.

Electrical Performance
Power distribution impedance was measured with both an HP 8510 Network Analyzer and an HP 4291A Impedance Analyzer over a range of 45 MHz to 1 GHz [2]. Figure 2 shows the measured impedance for several substrates with combinations of decoupling capacitance. The results indicated that there was minor difference between the IMPS power distribution structure and one using solid planes. Any planar effects were reported to be masked by attachment or wirebonding impedances and by the number and type of capacitors used.


 Figure 3. An IMPS BGA design can be executed with 2-metal layer-pair organic substrates.

High-Density MCM-BGA Application

In 1996, HiDEC, using flexible film and Tape BGA (TBGA) technology along with microvias and the IMPS topology was able to create an MCM-L with only two metal layers instead of the conventional four metal layers of an MCM-D [3]. This test vehicle puts two IMPS metal layers, which provide signal wiring and power distribution, on the two sides of a Kapton film. One side contains mounting pads to which the dies are wire bonded and discretes are soldered. This side is encapsulated. The other side has the lands in a ball grid array pattern. A part of the IMPS artwork is shown in Figure 3.

The test vehicle was built on two mil Sheldahl adhesiveless polyimide film, viaThin Ô . The basic design rules are 50 um lines and spaces, 150 um via target lands over 25 um laser drilled vias. The IMPS mesh consisted of 200 um lines and 50 um spaces, with the lines offset from the via row or column centers. Wirebond pads consisted of 200 um x 350 um rectangles on both metal layers, tied together with two vias.

 Picture4Figure 4. An IMPS topology before and after assembly.

The test vehicle showed conclusively that the IMPS topology could be applied to MCM-Ls and BGA substrates without the use of multilayering. Figure 4 is another closeup of the IMPS topology in a MCM-L.

In 1993, a large electronics OEM had the problem of having to redesign the control board of their largest 3 ½” hard disk drive. The boards were a standard 3.87” x 5.45” but their problem was that they wanted to cut a 2.8” diameter hole in the board so that another platter could be added to the drive. This would enable the drive to have a capacity of 16 GBytes, quite a capacity for 1993. The solution to the loss of nearly 5.8 sq. in. out of 17.5 sq. in. was to employ microvias and microvia-in-pads. The new microvia board (called Lynx) was designed with the reduced surface area and as a six-layer design (1+4+1), two less layers than the original.

Reading about the IMPS topology from HiDEC in 1994, the Lynx board was again redesigned to a four-layer construction. In order to minimize the microvias, the outer two layers (1 and 4) were flooded with ground and only power and signals were placed on the inner-layers. Figure 5 shows the new power-signal routing architecture, which was called Power Mesh to differentiate it from IMPS.

Picture5Figure 5. Power Mesh was adapted from the IMPS architecture but does not route GND bussing.

Electrical Model
The original Lynx board was not controlled impedance, but additional pcb designs that used Power Mesh were. The consensus is that Power Mesh is an offset coplanar stripline. Figure 6 shows this cross-section of the offset coplanar stripline. The table shows the values for 50 ohm single-ended and 100-ohm differential impedances for different trace widths, spacings, core thicknesses and overall thicknesses. The crosstalk model indicates that the Power Mesh Architecture creates a naturally low crosstalk condition. Each signal trace of X_width is approximately 3X or 4X distance from the next signal, depending on the power trace width. This creates horizontal crosstalk of less than 2%. The vertical crosstalk is extremely low. From 15 mV/V for thin cores (0.012”) to 2.6 mV/V for a thick core (0.051”).

Picture6Figure 6. The impedance and crosstalk model for Power Mesh is an offset coplanar stripline. The table presents single-ended and differential impedances for various traces and thickness

PMA Application
The first Power Mesh Architecture was completed in 1994. the Lynx multilayer is shown in Figure 7. The innerlayer FR4 core (fig 7a.) was 12 mils thick (0.012”). The initial design used epoxy-resin coated copper foil of about 2 mils thick as the microvia layers 1 and
4. The microvias were seven mils in diameter with 14 mil pads. Traces and spaces were 5 mils. Figure 7b shows the finished Power Mesh multilayer. Without any traces on the surface, as all components had via-in-pads, the unbroken ground plane serves as the effective ground return and impedance reference. It was also highly effective as a RFI/EMI shield. Switching noise was reduced because the ground connections were micro-resistance’s and had no inductive or capacitive elements in series to the ground connection. Similarly, noise budgets were improved because connection to power had the minimum inductance and capacitance, nearly 1/10 that of a through- hole and trace connecting the component land.

Designing With PMA
The one discouraging characteristic of the PMA is that EDA tools do not recognize nor automatically design with the Power Mesh Architecture. That does not mean you cannot design with PMA; it just means you must do it by hand. The process for designing a printed circuits with Power Mesh can be simplified to eight steps.

Picture7Figure 7. Example of a Power Mesh design. a. Innerlayer (L2 & L3) with buried vias b. Finished four- layer Power Mesh multilayer with microvia-in-pad and unbroken ground plane.

1. First build a special library for all fine and extra fine pitch geometry’s that include locations for blind via-in-pads.
2. Create the board stack up in the EDA tool for a four layer or 6-layer PMA.
3. Place all parts ( at a closer proximity). The critical factor in placing parts is to place the power pins and connections on a grid approximately equal to the Power Mesh traces center-to-center distance.
4. Break through all signal and power nets using blind vias- in-smt pads.
5. Protect all breakthrough vias so that they are not moveable.
6. Route the power traces to all power pins and connections and protect them. Route critical timing and clock lines and protect them. Then route the remaining signal nets on one innerlayer and only orthogonal routings on the other innerlayer. Buried vias are used to transition from one layer to the other.
7. Complete the Power Mesh traces to fill in missing legs and balance the Power Mesh over the entire boards surface. Blind vias need to be placed at each intersection of the same power levels (Vcc or Vdd) so that a Power Mesh results on the two layers that provides current distribution uniformly across the board. Clean up the board to minimize vias and trace length. Diagonal routing is o.k. now that routing is complete.
8. Expand all power traces (the Mesh) until they meet a signal trace or another voltage level trace. This will create the maximum surface area for the Power Mesh traces and increase the distributed capacitance between power and ground. Fill the outer layers with ground plane and then stitch the ground planes together where possible.

Picture8Figure 7. Example of a Power Mesh design. a. Innerlayer (L2 & L3) with buried vias b. Finished four- layer Power Mesh multilayer with microvia-in-pad and unbroken ground plane.

1n 1994, StorageTek, an OEM in Colorado, conducted performance benchmarking with microvia designs and fabrication [5]. The successes in that program contributed to their continued use of microvias. In 1998, it became apparent that they required some wiring model to indicate that a microvia structure was required. In performing that model development, a Power Mesh benchmark was designed for one of the microvia boards [6]. Figure 8 shows the two innerlayers of the four-layer Power Mesh structure and two of the six innerlayers from the original eight layer through- hole design. The wiring density model for the Power Mesh Architecture is:

Power Mesh = 17 to 40 signal inches per square inch per layer*

1. Calculate the Statistical Wiring density using Coors, Anderson & Seward [7]
2. Calculate the Manhattan Wiring Density using, Wd=0.0068(X)^2 – 0.1644(X) + 35.1, where X is the Coors Statistical Wiring Density.
3. Calculate the Routability Index for Power Mesh [6]
4. Calculate the Layout Efficiency using, L.E.(%)= 4.0642(RI)^-1.189, where RI is the Routability Index
* dependent on trace width and spacings

The new microvia topologies, IMPS and Power Mesh, have demonstrated their application to simplifying complex multilayer, PBGAs, and MCMs. IMPS can reduce the structure to a 2-metal interconnect, while Power Mesh uses a 4-Layer, reinforced laminate structure. These results show that these topologies have the capacity of positively impacting how electronic products are packaged and Interconnected.

1. L.W. Schaper, S. Ang, M. Ahmad, and Yee L. Low, "Theory and Experimental Conformation of the Interconnected Mesh Power System (IMPS) MCM Topology”, Proc. International Electronics Packaging Conference, Denver, CO, September 1994, pp. 462-469.
2. L.W. Schaper, S. Ang, Yee L. Low and Danny R. Oldham, "Electrical Characterization of the Interconnected Mesh Power System (IMPS) MCM Topology”, IEEE Trans. On Components, Packaging and Manufacturing Technology, Part B, Vol. 18, No. 1, February 1995, pp. 99-105.
Interconnection Application,” Proceeding of the ICE on Multichip Modules , Denver, CO, April 1994, pp. 188-192.

2. L.W. Schaper, S. Ang, Yee L. Low and Danny R. Oldham, "Electrical Characterization of the Interconnected Mesh Power System (IMPS) MCM Topology”, IEEE Trans. On Components, Packaging and Manufacturing Technology, Part B, Vol. 18, No. 1, February 1995, pp. 99-105.

3. L.W. Schaper, S. Ang, D.A. Arnn J.P. Parkerson, "A Low- Cost Multichip Module Using Flex Substrate and Ball Grid Array”, Proceeding of the ICE on Multichip Modules , Denver, CO, April 1996, pp. 28-32.

4. . L.W. Schaper, and Carl V. Reynolds, "Interconnected Mesh Power System, (IMPS) A Packaging and Interconnection Application,” Proceeding of the ICE on Multichip Modules , Denver, CO, April 1994, pp. 188-192.

5. R. Charbonneau, “A Comparison of Through Hole and Microvias in Printed Circuit Design,” The Board Authority- HDI (I), Vol.1,No.2, June1999, pp. 88-94

6. H. Holden and R. Charbonneau “Predicting HDI Design Density,” The Board Authority-HDI (I), Vol.2,No.1, April 2000, pp. 28-31

7. Coors,G, Anderson,P and Seward,L. "A Statistical Approach to Wiring Requirements", Proc of the IEPS, 1990, pp. 774-783 

 Go back to Contents


Section 4 Microvia Process Guidelines

Stan Heltzel, European Space Agency, ESTEC, Noordwijk, The Netherlands
Pierre Emmanuel Goutorbe, Airbus Defence and Space, Toulouse, France
Jean-Marc Guiraud, Thales Alenia Space, Toulouse, France
Thomas Rohr, European Space Agency, ESTEC, Noordwijk, The Netherlands

 stan heltzel

Stan Heltzel
Materials Engineer,
European Space Agency

High Density Interconnect (HDI) Printed Circuit Boards (PCBs) and assemblies are essential to allow space projects to benefit from the ever-increasing functionality of modern integrated circuits. The European Space Agency (ESA) in collaboration with its industrial partners have been updating their standards for PCB design, qualification, and procurement, which also include advanced PCB technologies such as microvias. Results from a wide range of microvia reliability testing have been obtained, which include modelling, assembly simulation, chamber thermal cycling, current induced cycling, and various other accelerated coupons tests.

In complement to the efforts on design, testing and modelling of various microvia configurations, the manufacturing processes have been reviewed in-depth as a result of weak microvia failures. This has been done in close collaboration with qualified PCB manufacturers and their chemistry suppliers. Corrective actions and various other recommendations have been listed in microvia process guidelines [1]. This can also be used for conducting a process audit with a level of detail that is still appropriate for general engineers without detailed chemical background. This paper presents the content of these microvia process guidelines, with the intention to provide support for the review of these complex processes.

High Density Interconnect (HDI) Printed Circuit Boards (PCBs) and assemblies are essential to allow space projects to benefit from the ever-increasing functionality of modern integrated circuits. Increasing demands for functionality translate into higher signal speeds combined with an increasing number of I/Os. To limit the overall package size, the contact pad pitch of the components is reduced. The combination of a high number of I/Os with a reduced pitch places additional demands onto the PCB, requiring the use of laser drilled microvias, high aspect ratio core vias and small track width and spacing. Manufacturing methods and acceptance criteria are adapted for the low series production as relevant for space projects. While the associated advanced manufacturing processes have been widely used in commercial, automotive, medical and military applications, reconciling these advancements in capability with the reliability requirements, remains a challenge for all industry [2] and in particular for space.

stacked vias stackedvia 2

Two via configurations of 3 layers semi-stacked internal and 2 layers staggered

The European Space Agency (ESA) in collaboration with its industrial partners have been updating their standards for PCB design, qualification and procurement [3, 4]. These include new test and inspection methods for qualification and for lot conformance, as well as more detailed descriptions of PCB technology features and their acceptance criteria. Electronic assemblies for space are not only subject to the environmental conditions of ground, launch and space operation. In addition, PCBs need to withstand a relatively high amount of assembly operations that can occur to ensure reliable solder joints and the correct functionality. The new standards address concerns from previous failures, such as imperfections in dielectric materials, cracks or contamination, which can cause latent short circuit failure due to Electro Chemical Migration (ECM) [5]. Another key reliability aspect is the absence of barrel cracks and interconnect defects to ensure reliable (micro)via performance. Because of the risks associated with the technological complexity of HDI PCBs, this technology was so far not covered by specific requirements from the European Cooperation for Space Standardization (ECSS). Having set a robust framework of test and inspection methods for standard technology, the recently updated standards also implement advanced PCB technologies such as microvias. This coincides with the funding of the technology development and qualification of HDI PCB assemblies. Results from a wide range of microvia reliability testing have been presented in [5, 6, 7], which includes assembly simulation, chamber thermal cycling, current induced cycling and various other accelerated coupons tests. This is supported by the modelling of different designs, assessing the impact of the location of the microvia with respect to each other and with respect to the buried via. The wide combination of tests, the consolidated designs and the collaboration with international partners intend to generate a robust dataset for the use of HDI PCBs in future space projects.

In complement to the efforts on design, testing and modelling of various microvia configurations, the manufacturing processes have been reviewed in-depth as a result of weak microvia failures. This has been done in close collaboration with qualified PCB manufacturers and their chemistry suppliers. Corrective actions and various other recommendations have been listed in a microvia guideline document [1] that can also be used for conducting a process audit. This paper presents the content of these microvia process guidelines, with the intention to provide support for the review of these complex processes

General process overview and recommendations
The microvia process guidelines provide recommendations for each of the main process steps of microvia manufacturing, which are the following: laser drilling, pre-etching, desmear, electroless copper, flash plating, and via fill plating. In addition, microetch is typically implemented within the process line after desmear, prior to electroless copper and prior to via fill plating, as well as in the pre-etch process. Rinses are implemented in most process steps, as well as pre-dip and post dip baths.

It is considered that laser drilling and copper filling are the baseline for microvia manufacture (as opposed to mechanical drilling and resin filling). While these guidelines state a preference for horizontal processing, many recommendations are targeting vertical processing because this is most widely used. Some specified recommendations may be advantageous for the reliability of microvias, whereas there might be consequences or disadvantages for other aspects of PCB manufacturing processes. These guidelines prioritize the microvia reliability and specify recommendations to processes, as well as inspections or test methods for initial qualification, periodic in-process verification and for lot conformance.

Microvia manufacturing should occur separately from mechanical via manufacturing. This allows for optimization of desmear, microetch and electroless copper for the microvias, without consideration to the mechanical vias. The main disadvantage of doing so is thicker plated copper layers, which can be a problem for fine line etching. Another possible disadvantage is longer processing time.

A horizontal desmear/microetch/electroless copper/galvanic line is preferred over a vertical line, as it allows more accurate process control. Horizontal equipment provides better solution exchange due to flood bars and ultrasonic bars. Vertical equipment needs special features like vibration and shocking. A disadvantage might be that horizontal processing offers less flexibility and requires higher investment. In addition, conveyorized systems are available for both horizontal and vertical set-up and their use is recommended.

For vertical lines, racks are preferred over baskets. Spacers on baskets should ensure consistent positioning and be subjected to periodic verification. Mechanical wear on spacers should be prevented as it alters the positioning, as well as it dampens the mechanical movement from vibrations. Because small spacing can restrict chemistry flow, process performance should be verified in these conditions. The margin with respect to the implemented minimum spacing should be investigated.

A daily inspection of mechanical aspects of the line should be performed, including vibration systems, handling systems, nuts, bolts, racks, baskets, spacers. This is in addition to the verifications of the chemistries and bath conditions. The line, transport racks, baskets, tanks, pipes, overhead lighting, ceiling and surroundings should be clean. Periodic verification of cleanliness and a routine maintenance schedule should be in place.

Pre-dip and post-dip baths can contain (intentionally) small amounts of active process chemistry from previous or subsequent processes. These baths should be treated equally critical as an active bath for its process control, monitoring of contamination and replenishment. These baths should be run as a dynamic process (i.e., with agitation).

Process guidelines from the laminate supplier should be taken into account. They may need to be adjusted to accommodate the specific set-up and technology.

An audit from the chemistry supplier should be performed for each part of the process line. This should be performed by a (senior) expert. It is recommended that the auditor is not the same person that recently performed the (initial) installation of the line or that conducts periodic maintenance. Critical as well as non-critical recommendations from the chemistry supplier should be implemented.

General verification
The maximum overhang, glass fibre protrusion, aspect ratio, diameters on top and bottom should be covered by the qualification. The efficiency of chemistry flow in microvias should be verified for all processes taking into account the (highest) density and aspect ratio of microvias. A high density of microvias can consume a large part of active components of the chemistry locally in the bath. Such verification can be performed by characterizing the deposit, cleanliness and general aspect. It is not possible to measure chemistry constituents inside the microvias.

failure modes
Adhesion between target pad, electroless copper, flash copper and via fill copper should be verified periodically, for instance by pull test and/or by thermal stress and destructive physical analysis (DPA). Adhesion between various copper layers depends on continuous crystal growth across the interfaces. This is named epitaxy. A qualitative assessment should be performed periodically, for instance by using scanning electron microscopy (SEM), focused ion beam (FIB), electron backscatter diffraction (EBSD), X-ray diffraction (XRD), electropolishing and/or ion beam polishing. The polishing process for microsections smears copper, which can mask cracks. Chemical micro-etch removes smear but shows plating boundaries and does not allow one to evaluate the presence of cracks or interconnect defect. Ion beam polishing is a relatively simple bench top technique that is efficient at showing such defects, as can be seen in figure 1.

ion beamFigure 1: Cross-section of a microvia in as-polished condition (left), sharpened to show a hint of a crack between plating boundaries (red arrows); after microetch (middle) and after ion beam cleaning (right)

Verification of process performance should cover the minimum and the maximum of process parameters, including temperature, dwell time, additives, contaminants, bath age. This is usually done by the chemistry supplier for the initial set-up. The process parameters can be modified by the PCB manufacturer in conjunction with the chemistry supplier to tailor for the specific technology to be manufactured, in which case the changes should be verified. Verification should be performed across the panel to investigate if the center and edges of the panel receive equal process efficiency. Also, dependency with circuit and hole pattern should be investigated. This should be done for initial qualification and it should be repeated periodically. Verification should be performed on multiple panels within a job load (in basket or rack) as well as from batch to batch. Verification should be performed to cover the qualified design features (such as diameter and aspect ratio). It is considered good practice to perform verification of more complex features than what is covered by the qualification to assess the margin.

Laser drilling
The opening of surface copper may be done by laser or by wet chemistry. Microvia holes should be drilled in the dielectric using lasers, not with mechanical means. The efficiency of laser ablation through resin and through glass determine the shape and dimensions of the microvia. This should be verified per batch, for instance using microsectioning, SEM and/or 3D microscopy.

In addition, an in-process top-down inspection of the microvia target pad should be performed periodically by SEM to verify that the organic residue and recast copper on the target pad is within nominal limits. Such limits may be provided by chemistry/process suppliers or by experience from the PCB manufacturer.
The laser drilling should result in a straight hole wall, to maximize the contact area to the target pad and to avoid a ‘barrel’ shape. Alternatively, the hole wall can be slightly inclined (e.g. maximum 20°) which generates a slightly conical shape of the microvia. This can be beneficial for chemistry flow (even though the inclined hole wall reduces the contact area to target pad). Inefficient drilling typically leaves the second glass weave (when using 2 prepregs) partly uncut, which causes a very conical hole wall that reduces contact area to target pad, as can be seen in figure 2, or an irregular barrel shape that is not favourable for chemistry circulation during subsequent plating steps.

After laser drilling, there should be another laser process (defocused UV clean step, named UV skiving, or alternatively a CO2 cleaning step) for the cleaning of the target pad (internal pad), similarly to desmear. In case of UV skiving, this can slightly ablate the copper. The power of the laser should be verified to be high enough to perform the cleaning, but low enough to avoid softening or otherwise altering the copper of the target pad. Softening the target pad during this process can result in the fixation of ash, carbonization, resin debris to the target pad, which is the opposite effect of what the process intends to do.
Laser drilling should avoid copper overhang on the external pad (capture pad) because this is not easily removed by subsequent processing. Overhang limits the chemistry flow. An additional copper etch process may be implemented. This can remove a slight amount (few μm) of overhang but not a significant amount. The main purpose of copper etch is cleaning off the target pad. The morphology of the copper foil of the target pad should not be altered by the laser drilling or cleaning in a way that reduces adhesion of electroless copper. Laser drilling creates a lot of heat that can affect the copper morphology on the target pads. Therefore, laser drilling should follow a non-optimized (for speed) pattern that allows to cool before drilling the adjacent hole. The slight disadvantage of this is extended process time. This precaution may not be necessary in case the power of the laser has been verified not to cause heating or alteration of the copper. The penetration depth to the target pad of laser drilling and laser cleaning should be specified and subject to periodic verification. A slight penetration may be expected for a UV laser, whereas no penetration is expected for a CO2 laser. Penetration generates recast copper. Absence of breakout from target pad or penetration should be verified by visual inspection or X-ray scanning.

Registration of drilled hole to the target pad and to the external pad should be verified by microsectioning and measurement of annular ring in x- and y-directions on all 4 corners of a panel. The procedures should specify the allowable wait time after laser drilling until subsequent processing (pre-etch). Generally, there is no criticality expected from this wait time, but it is good practice to specify it in procedures.


Figure 2: Cross-section of a microvia with reduced contact diameter to target pad because
the laser was not able to cut efficiently through the second glass layer.

The pre-etch process should be implemented prior to desmear. Pre-etch should be performed using peroxide or persulfate and is best accomplished using a horizontal process line. It is implemented prior to desmear to remove recast copper and organic contaminates without being overaggressive to the copper of the target pad. This will reduce macro-roughness.

On horizontal pre-etch equipment, depending on their design, panels should be processed twice and turned over to compensate for differences from top to bottom and to ensure all microvias are equally processed. It should be carefully evaluated that a double pass does not cause a too high amount of much etching.

High pressure water cleaning should be implemented. Mechanical brushing (as done for through going hole vias) should not be performed at this stage of microvia manufacturing. After pre-etch, panels may be dried, and a wait time may be implemented. The maximum wait time should be specified in procedures. A wait time, without drying should not be performed.

desmearThe desmear process is critical. Inadequate adhesion between electroless copper and target pad is an important failure mode of microvias. A desmear cleaning process should be implemented to clean target pad (and hole walls) after laser drilling. Desmear may be performed using plasma. The efficiency of plasma desmear should be specifically verified across a panel, and from panel to panel depending on its position inside the chamber. Desmear should also be performed using wet chemistry (permanganate). A combination of both should typically be performed, in which case plasma should occur before wet chemistry, because wet chemistry can help removing remove ash residues from the plasma process.
vertical panels
Cleaning (and swelling) in solvent should be implemented prior to chemical desmear, either as a pre-clean step or as the first active process within the desmear line. This should include ultrasonics in a horizontal set-up, or vibrations in a vertical set-up. The power of the ultrasonics or vibrations should be periodically verified.

On vertical chemical desmear equipment, panels may be processed twice to ensure all microvias are equally processed. On horizontal desmear equipment, panels should be processed twice and turned over to compensate for differences from top to bottom. Some equipment may be already compensating for this.

It should be verified that permanganate cannot dry inside microvias during the maximum drip time permitted to the process. Possibly, drip time should be minimized after consulting with the chemistry supplier. Sodium permanganate is recommended since it has better solubility than potassium permanganate and is, therefore, more easily removed by the neutralizer.
wear of rackThe efficiency of the desmear process should be verified across the panel, among panels of a job load (basket or rack) and among batches. Periodic, e.g., daily, weight loss measurement on test samples of applicable laminate types should be done to ensure process efficiency. To accurately measure the expected low amount of weight loss, it is essential to implement a strict measurement protocol, including bake out, elimination of static charge, environmental control of relative humidity and temperature. The protocol can be obtained from the chemistry supplier. The weight loss values should be determined taking into consideration the materials, technology and equipment set-up.

The typical chemical desmear neutralizer is of the non-etching type. Alternatively, hydrogen peroxide and sulfuric acid neutralizer is available and has a side reaction that etches copper from the target pad. In this case, the etch rate and other process parameters should be verified in the same way as microetch. A separate step for glass etch or glass frost may be implemented after desmear. This can be included in the neutralizer.

The maximum wait time after desmear prior to subsequent processes (microetch and electroless copper) should be verified by the qualification.

Microetch is equally critical as desmear, as these processes determine the surface preparation of the target pad, among others. Microetch should be implemented a) before desmear (named ‘pre-etch’), b) after desmear within its process line, c) prior to electroless copper within its process line and d) between plating processes (flash and via fill and pattern/panel plate). A pre-wetting stage should be implemented prior to microetch. In case processes run wet to wet (without drying), this is already accounted for.

smooth aspectPersulfate may be used for microetch to remove film layers from the conditioning and activation processes (e.g. for plated through-hole manufacturing) and to increase the surface topography by exposing the copper grain structure. This will increase micro-roughness. Sodium persulfate or potassium peroxymonosulfate is recommended for its stable etch rate.

Vertical microetch should be performed in a bath including vibrations, oscillations and a pump that ensures circulation and filtration of the bath with accurate flow control. This is to ensure efficient chemistry flow inside the blind microvia holes and uniformity across the bath. An air sparger (bubbles) on both sides of the panel can be used to further improve chemistry flow. In addition, ‘educator’ systems are available that ensure circulation inside the microvias by ‘venturi’ effect. Also, a ‘hammer’ system is in use that provides a mechanical shock, similarly to vibrations. Vibrations should be measured on panels periodically to ensure efficient transfer of mechanical energy. The lack of mechanical clamping of racks and panels, or the spacers in baskets, can dampen vibrations. The measurement may be done in air, as measuring in liquid chemistry may be difficult.

microetchEtching efficiency inside microvias should be verified periodically across the panel and from panel to panel depending on its location in the bath. Longer process time at a lower etch rate typically provides better uniformity across the panel. Etching efficiency can be verified for instance by roughness measurement or penetration depth measurement using DPA and top-down SEM imaging. The copper roughness on target pad is the result of laser, pre-etch, desmear and microetch. Copper roughness on intermediate plated copper layers (e.g. flash copper) is the result of microetch only. Etch rate on the surface of a test sample should be verified prior to each working shift. The etch rate coupon should be used only once because the measured etch rate will change on a single, aged coupon. Procedures should specify if the coupon needs to be pre-cleaned and what possible effect such surface preparation may have on the etch rate measurement. Plated copper etches at a different rate than copper foil (that is typically of type ED electrodeposited). The correlation between the etch rate of a test sample and the etch rate of copper plating (that is on the surface of the target pad) should be established.

excessiv etch  evaluation 

The surface condition (roughness, cleanliness) inside microvias should be established for the minimum and maximum etch rate on test samples. This should be done in consultation with the chemistry supplier. A certain minimum etch rate ensures proper cleaning, while maximum etch rate prevents the occurrence of wedge voids in corners due to the recessed target pad.

Bath components and copper build-up in the microetch bath should be monitored. For instance, sulfuric acid can change copper morphology without having much impact on etch rate. There should be no wait time, and no drying after microetch prior to subsequent processes (electroless copper or plating). The priority level in the automated process control software should ensure this. To prevent oxidization, extended rinsing should not be performed if this is to replace wait time (in air). However, slight oxidation is possible to be removed by catalyst pre-dips.

vertical rinsingRinse processes should be implemented in almost all main process steps. Each process step should have its own dedicated rinse. Cross contamination to other baths should be prevented by cascade rinse and/or counterflow rinse. Alternatively, a high rinse flow on a single bath may also be efficient. Efficiency of rinsing should be verified by investigating the dilution factor and cleanliness of the final rinse bath. Typical dilution factors are 2000 to 10000.

Critical vertical rinse processes should include vibrations, oscillations, pH-control, filtration and a pump that ensures circulation of the bath with accurate flow control. In addition, an air sparger (bubbles) on both sides of the panel may be used in rinse processes after microetch. In addition, some rinsing may be static and/or spray rinse. Vibration should be measured on panels periodically to ensure efficient transfer of mechanical movement. This verification can be done in air, but it might be difficult to do in liquid. Rinse flow meters should be installed on each bath separately and allow for accurate flow monitoring.

Rinsing after catalyst prior to electroless copper should be acidified to prevent oxidation. Rinsing after microetch should be acidified to prevent deposition of copper oxide. This should be implemented only if it is in-line with the recommendations from the chemistry supplier.

Periodically, e.g. once a week, the rinse baths should be emptied, cleaned and completely renewed. Cleaning should ensure the removal of any algae and other contamination. The effect of running rinses at maximum age should be verified.

Electroless Copper
It is preferred to run wet-in-wet processes from microetch to electroless copper. In case this is not done, it is important to implement an initial wetting step in the electroless copper process. The electroless copper process should be efficient to deposit electroless copper on all of the hole wall of all microvias in one single pass of the process. A double pass is an alternative to patch up process inefficiencies, such as non-uniform deposition or poor adhesion. Double pass can be performed on older equipment (that are less efficient to deposit electroless copper in all microvias in one pass) and for manufacturing through-going hole vias. This is one of the reasons why microvias should not be processed at the same time with through going hole vias that may need double passing.

There is a very strong relationship between conditioner, catalyst, accelerator/reducer and electroless copper. A change in one step has impact on other process steps and should, therefore, be subject to verification. The efficiency of rinsing after conditioner, catalyst and accelerator/reducer should be verified. In addition, it should be verified that rinsing is not excessive. Long rinsing of conditioner can reduce the conditioner’s efficiency. Long or incorrect pH rinsing of catalyst can cause particulates (or insoluble hydroxides) that could deposit on copper surfaces and reduce adhesion.
separationDeposition rate inside microvias should be correlated with deposition rate obtained on the test sample. This is named throwing power. This verification can be achieved, for instance, by overplanting with nickel (galvanic or electroless) to avoid smearing of copper (during microsectioning) and subsequent SEM analysis. The deposition rate should be verified using the test sample prior to each working shift. The sample laminate of the test sample should be used only once, because the measured plating rate on an aged sample will change. The sample should be of the same laminate as the technology to be manufactured and copper cladding should be etched off.

ec copper
The procedures should specify the minimum and maximum electroless copper deposit thickness inside the microvia holes. This should be verified periodically. The efficiency of electroless copper deposition should be verified across the panel, among panels of a job load (basket or rack) and among batches. Electroless copper deposition should be determined on the hole wall and on the target pad. The target pad typically receives less electroless copper thickness, which is deemed beneficial for reliability. Electroless copper deposition can be determined for instance by cross-sectioning and SEM, possibly using overplanting (for instance with nickel), or by a back-light test. The efficiency of electroless copper deposition should be verified for the used aspect ratio, overhang and pitch.
double passThe electroless copper adhesion to target pad should be verified periodically, for instance by pull test or thermal stress and DPA. The morphology of electroless copper should be verified and compared to the target pad and plated copper. Aligned grain boundaries and visible interfaces are an indication of poor joint integrity. The aspect should not be amorphous. Top-down SEM inspection is preferred over cross-sectioning to avoid polishing artifacts and because it allows to inspect a larger surface area.

There should be no wait time, and no drying after electroless copper prior to subsequent processes (flash plating). It should be verified that the time to transfer to subsequent flash plating is minimized to prevent drying, oxidation or contamination of electroless copper inside microvias.

Palladium (as a preparation to electroless copper) deposits mainly on dielectric and to a much lesser degree on target pads. Rinsing should be implemented after palladium process; in which case it is not expected that palladium can affect the epitaxy/crystal growth of electroless copper compared to the target pad.

Alternative metallization processes to electroless copper can be in use, such as direct metallization. But this is not currently the case for ESA qualified PCB manufacturers [8].

Copper plating
Microvia copper plating includes flash copper, via fill copper, pattern and panel plating processes. Plating uniformity should be verified across the panel, among panels of a job load (basket or rack) and among batches. Plating uniformity is affected by current density, and thus the pattern design of surface copper and microvia pitch. This interdependency should be specifically verified by determining minimum and maximum plating on patterns with low and high current density.

plating cellsWaiting time in galvanic bath after the nominal duration of plating should be avoided. Zero current can result in reversed or unexpected plating and cause deposition of contaminants on the freshly plated copper layer. Care should be taken that residual low current does not result in different copper crystallographic structure. Maximum duration for residual low current should be specified and substantiated by characterization of the copper. Full current is recommended for microvia reliability, but it has the disadvantage of plating thick copper (on surface).

There should be no wait time, and no drying after flash plating prior to subsequent processes (via fill plating). In case this is not done, there should be significant cleaning and microetching, e.g., about 1-2 μm. The thickness of flash plate should be sufficient to sustain such amount of copper removal. As an alternative, in case of pattern plating at the same time of microvia fill plating, care should be taken to ensure the acid cleaner (pre-dip) and microetch processes remove any residue from the imaging process. It is possible that flash plating is combined with via fill plating into a single process.copper failure

In complement to various efforts on design, testing and modelling of microvia reliability, microvia process guidelines have been issued. This document [1] intends to provide best practices, with a level of detail that is still appropriate for general engineers without detailed chemical background. The document aims to support the review of microvia manufacturing processes or to conduct a process audit.

The microvia process guidelines could not have been realized without the in-depth support from the chemistry suppliers. The authors like to thank R Massey, K Wurdinger, T Aillas from Atotech; S Sullivan, C Colangelo from DuPont; W Bowerman, R Bellemare from MacDermid Alpha.

[1] ESA-TECMSP-TN-19672, Microvia process guidelines, 2020
[2] IPC-WP-023, IPC Technology Solutions White Paper on Performance-Based Printed Board OEM Acceptance: Via Chain Continuity Reflow Test: The Hidden Reliability Threat - Weak Microvia Interface, 2018
[3] ECSS-Q-ST-70-12C, Space product assurance - Design rules for printed circuit boards, 2014
[4] ECSS-Q-ST-70-60C, Space product assurance - Qualification and procurement of printed circuit boards, 2018,
[5] Advanced PCB technologies for space and their assessment using up-to-date standards, S. Heltzel, ECWC15, 2020, Shenzhen, China
[6] High-density PCB technology assessment for space applications, M Cauwe et al., IPC APEX EXPO, 2020, San Diego, CA, United States
[7] Round robin testing of HDI technology from space-qualified PCB manufacturers, M Cauwe et al., IPC APEX EXPO, 2021, San Diego, CA, United States

“This paper and Presentation "Microvia Process Guidelines" was first presented at the 2021IPC Apex Expo Technical Conference and published in the 2021 Technical Conference Proceedings”.

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Section 5

AGM and Technical Seminar

 March 2nd 2022

Emma HudsonICT Chair

A two-year project funded by an Innovate UK SMART Grant aims to reduce the impact of e-waste using naturally derived, biodegradable and nontoxic products. Those attending the webinar for the Institute of Circuit Technology’s annual meeting on March 2 learned more about the project, as well as statutory paperwork obligations as of the UK REACH regulations.

Following the formal business, ICT Chair Emma Hudson introduced and moderated this technical webinar, which brought a final update on the progress of the ReCollect project and discussed the legislative implications of the UK REACH regulations.


Jack HerringChief Product Officer,
Jiva Materials

The ReCollect Project

ReCollect (Efficient Manufacturing of Recyclable Composite Laminates for Electrical Goods) was a 30-month project funded by the Innovate UK SMART Grant scheme and led by Jiva Materials, partnered with Coventive Composites. The ReCollect project aims to reduce the impact of the e-waste stream using naturally derived products, biodegradable and non-toxic.

Proposed as an alternative way of managing end-of-life circuit boards, the project is focused on removing glass fibre and epoxy resin from the supply chain by the use of a novel recyclable laminate technology known as "Soluboard," based on woven natural fibre reinforcement and a polymer soluble in hot water. At end-of-life, this material can be recycled simply by immersing it in near-boiling water, causing the polymer to dissolve, enabling the fibre reinforcement to be easily separated for reprocessing or composting, and the electronic components and circuitry to be recovered intact.

The primary objective was to demonstrate the feasibility of producing a PCB substrate in high volumes with performance comparable with CEM-1 and FR-4 within the UK. The secondary objective was to ensure that this substrate was compatible with existing aqueous etching and plating processes used in PCB fabrication. ICT had provided dissemination and industry feedback. The project has now ended and Jack Herring, managing director of Jiva Materials, gave a meaningful summary of what had been achieved.

Herring described the initial target market as commodity PCBs in domestic equipment, waste from which constituted 32% of WEEE. Products included PC peripherals, power circuits, and LED lighting. He reminded the audience that the WEEE directive placed the responsibility for waste recovery on the manufacturer of the product, and that Soluboard PCBs could be removed for recycling from products recovered through WEEE take-back schemes.

Considering carbon savings, he stated that the carbon footprint of one square metre of Soluboard is equivalent to 7.1 kg of CO2, compared with 17.7 kg for a similar square metre of FR-4, representing a 60% reduction. And the plastic saving of Soluboard compared with FR-4 is 620 grams per square metre. A selling price equivalent to that of FR-4 can be achieved, and the material can be supplied in the form of a copper-clad laminate for PCB fabrication or an unclad laminate for printed electronics applications.

It had been demonstrated that Soluboard is compatible with industry-standard wet processes for PCB fabrication. It is straightforwardly drilled and routed, and PCB assemblies can be successfully soldered with low-temperature alloys. Herring showed examples of boards for power supply units produced by print-and-etch technology, with thermally cured solder resist. A further example was boards for LED lighting, engineered to achieve the required reflectivity levels. In a printed electronics context, unclad Soluboard has been used to produce boards for Arduino microcontrollers using industry-standard functional silver inks.

Preliminary technical data sheets had been prepared with a comprehensive listing of mechanical and electrical properties. The material has a flammability rating equivalent to UL94V-0, and is expected to be formally recognised shortly.

Looking Ahead
Herring discussed future plans. The original target market was commodity PCBs—single- and double-sided without plated through-holes—and this technology level had been reached within the Innovate-funded ReCollect project. Moving forward, it is intended to address multilayer applications. One exciting prospect is Dell Technologies’ Concept Luna, in which Dell is exploring ways of reducing the carbon footprint of its products to make them re-usable and repairable before finally recycling materials and components. Dell has shown definite interest in “a new bio-based printed circuit board made with flax fiber in the base and water-soluble polymer as the glue,” Herring said, and Jiva is looking forward to becoming a collaborator in the project.

In terms of substrate development, the first version of Soluboard had a relatively coarse-weave jute-fabric reinforcement. A finer-weave fabric enabled improved electrical properties and would form the basis of a second-generation laminate. The solubility of the resin component clearly presented some obstacles to be overcome when aqueous plated through-hole chemistries were encountered, and this was a further area of development to be tackled once more funding was secured. Another topic of interest was in-mould electronics, where the thermoplastic properties of Soluboard make it an appropriate choice, and efficient recycling equipment to process Soluboard recovered from take-back schemes will be developed.



Colin MartinSenior Partner,
Parachem Consulting Chemists

A Systematic Approach to Regulations

Continuing on a theme of chemical conscientiousness and the exciting world of legislation, we were reminded by Colin Martin, senior partner at ParaChem Consulting Chemists, of our statutory responsibilities under the REACH (registration, evaluation, authorisation and restriction of chemicals) regulations.

REACH was formed in 2007 as a European chemicals’ regulation aimed at improving the protection of human health and the environment by identification of the intrinsic properties of chemical substances. The UK formally left the EU on 31 January 2020 (“BREXIT”), so the EU REACH regulations were no longer legally binding. They were replaced by UK REACH, a new statutory requirement to disclose information about the composition of manufactured “articles,” and disclosure requests would still travel up the supply chain from any EU companies.

The UK government department responsible for REACH is the Department for Environment Food and Rural Affairs (DEFRA), which carried out a survey to establish the status of UK industry with regard to REACH compliance. It concluded that there was little understanding by manufacturers of REACH and its consequent obligations. Most of industry was not aware of the regulations or their implications, even though it was actually a criminal offence not to comply with disclosure duties. Having just published the results of their survey, DEFRA is now taking an active stance on REACH, and its regulations will be enforced.

What happens next? Martin set out to disentangle the complexities of the procedures and present a systematic approach to compliance. He emphasised that, although this will involve a commitment of resources, it need not be overwhelming if the exercise is tackled methodically. It is necessary to compile a database providing data on “substances of very high concern,” (SVHC) in manufactured articles. The database will need to include inventories of all manufacturing consumables and all manufactured or bought-in items, with SVHCs identified and their mass percentages calculated. The minimum information required to provide to the consumer is the name of the SVHC, and this needs to be provided within 45 days. Specialist proprietary software is available to help in managing the database.

Martin gave an example listing of all consumables and their compositions, and then looked specifically at the individual components of a particular product, with the composition of a fictitious proprietary solder mask used for illustration. The concentration of each of these consumables in the product was determined. Similarly, his inventory of articles listed all the ingredients used in the manufacture of each article and their mass percentages.

Once all of this data-gathering had been completed, it provided a resource from which five categories of formal report could be prepared: UK SVHCs at concentrations greater than 0.1% contained in individual articles, similar for EU SVHCs, customer reports of UK SVHCs contained in articles, similar for EU SVHCs, and a European Chemicals Agency report if more than 1,000 Kg of any SVHC was being processed in a year.

As one who had enjoyed a career coming to terms with the technicalities of actually manufacturing printed circuit boards, I was reminded that today’s statutory paperwork obligations extend far beyond routine production and quality assurance documentation.

Pete Starkey

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Section 6

ICT Winter Seminar Review: Nov 2021


Pete StarkeyTechnical Editor,
Faced with the choice between a real or virtual event, Bill Wilkie took a calculated risk. It has been many long months since members of the Institute of Circuit Technology had gathered together under one roof, but a fair-sized bunch of industry stalwarts braved the weather and the threat of COVID, descended on the Manor Hotel in Meriden, UK, on November 30, and applauded Bill’s decision to go live. They were not disappointed; the program was superb, the atmosphere upbeat, and the networking opportunity priceless. 




 Sales Account Manager,
Nikon Metrology

Advances in X-ray Metrology

The first presentation came from Richard Frisk, sales account manager with Nikon Metrology, who gave a fascinating introduction to recent advances in X-ray inspection systems, particularly regarding their applications in solder joint inspection but with many examples of their ability to examine the finest details in all kinds of electronic and mechanical structures.

Frisk briefly introduced the company, which had three other specialist divisions: imaging products, semiconductor lithography systems, and healthcare, in addition to their interests in industrial metrology. He commented that the Nikon name derived from “Optics from Japan.”

Although X-ray imaging systems had been used for many years as an aid to PCB manufacturing, their main historic application had been for checking registration in multilayer boards. There had been many advances in capability over the last 20 years and Frisk described three types of X-ray image that had particular uses in solder joint inspection: radiography, computed tomography and laminography. He emphasised that, for metrology, good image quality was the basis for accurate measurements.

Using radiographs of a soldered BGA device, he demonstrated how radiography was used to detect and measure voids in the solder joints, explaining that it had become normal practice to invert the image so that the denser the material the darker it would appear and voids would show as light within a dark background.

A view with the X-ray source and detector normal to the PCB showed clearly defined solder balls and bond wires. Some solder balls showed evidence of voids and it was possible to calculate the percentage of solder ball area to void area and apply accept-reject criteria to the images.

An oblique view gave the effect of seeing the image in perspective and enabled voids to be further classified as “near to the PCB-solder interface,” “near to the IC-solder interface” or “mid-ball,” and features like poorly formed solder joints and head-in-pillow type defects could be identified.

Resolution was high enough to enable wire-bond and die attach inspection, and the examination of individual balls. Typical X-ray settings were 110 kilovolts and 130 microamps.

He showed several analysis examples and inspection algorithms for BGA devices, although he commented that radiographs could get very “busy” and needed a skilled operator to make judgements.

Computed tomography was a scanning process whereby the sample was continuously rotated whilst thousands of X-ray images were taken and then reconstructed by a powerful computer into a three-dimensional volume from which two-dimensional slices could be sectioned in any direction and a three-dimensional model generated, enabling in-depth automated defect analysis and measurement at high resolution. Individual materials could be colour-coded and Frisk’s examples of the structure of QFP and BGA components were spectacular in their detail.

With flat samples such as PCB assemblies, a limitation of computed tomography was the distance that could be fully penetrated as the sample was rotated parallel to the X-ray beam. In comparison, laminography was a non-destructive inspection technique for samples of any size that enabled the virtual micro-sectioning and analysis of large boards with typical scan times of less than five minutes. Laminography could be used to view defects in multi-layer PCB assemblies and devices and for early identification of latent defects.

Frisk held the audience spellbound with some video examples of fault-finding and forensic applications which demonstrated the capability and versatility of currently available X-ray equipment.




Jiva Materials

 A Solution for E-Waste?

“The world’s first recyclable PCBs” were features of the presentation by Dr. Jonathan Swanston, CEO of Jiva Materials, originators of the Soluboard recyclable PCB substrate.

Swanston began with the frightening statistic that 54 million tons of waste electronics and electrical equipment are produced world-wide annually, and the quantity continues to grow. His figures indicated the UK alone to be responsible for generating the equivalent of 23.9 kilograms per person, a total of 727,000 tons, and that 32% of all e-waste consisted of small domestic equipment.

Against that background, he described the characteristics of Soluboard, a composite laminate based on natural materials bound by a non-toxic and biodegradable resin soluble in hot water, with physical properties comparable to those of market leaders.

The carbon footprint of one square metre of Soluboard was equivalent to 7.1 kg of carbon dioxide, compared with 17.7 kg for one square metre of standard FR-4, indicating a 60% reduction in carbon footprint and a saving equivalent to 620g of plastic per square metre compared with FR-4.

Swanston described two versions of his material, a copper-clad laminate for subtractive processing, with woven fibre reinforcement based on jute, and a bare laminate for printed electronics with woven fibre reinforcement based on flax. The manufacturing sequence for the unclad version followed similar impregnation, drying, layup and press lamination stages to those used in conventional laminate production. Copper foil could be subsequently press-bonded to unclad material using an adhesive. The process stages for producing PCBs were basically similar to standard practice. Conductive silver ink was used for assembly of printed electronics substrates and low-temperature solder for etched circuits. He showed an example of a fully assembled prototype single-sided Arduino board produced by Jiva Materials.

It was believed that the mechanical and electrical properties of Soluboard would meet the requirements of most sectors within the electronics industry. Testing to IPC standards was in progress and expected to be completed shortly, with UL recognition to follow during 2022. Jiva’s initial target market was a share of the 2.8 billion square metres of FR-4 currently used in single and double-sided boards for domestic appliances.




Senior Research Scientist,

Electronics Research Projects

Although gaining access to the third presentation may have tested Bill Wilkie’s IT skills, his efforts were rewarded when the connection was successfully made and a virtual presentation was received online from Martin Wickham, senior research scientist at the National Physical Laboratory.

It was clear that there was a lot going on at NPL. Wickham gave an update on a busy program of new electronics research projects meeting current challenges in electronics reliability. Smaller, lighter, faster, cleaner, smarter, hotter—these were the inevitable buzzwords, reducing CO2 emissions toward “net zero” was a major driver and there was general push toward higher voltages.

One of the main projects in the 2021-2022 program was the continuing study of high voltage “partial discharge” effects, which could occur as a “spark” in the insulation between two conductors at a point where the electric field exceeded the local dielectric breakdown strength and was often associated with minor defects in the dielectric. Partial discharge could occur multiple times at lower voltages and progressively reduce the breakdown strength of the insulation. A multi-channel test system had been developed and used for an initial evaluation of partial discharge and insulation resistance at high voltage. The system could operate at voltages up to 10,000V. Work to date had concentrated on twisted pairs representing motor insulation but would shortly be extended to include PCBs.

The second phase of the ongoing study of conductive anodic filament (CAF) effects at high voltages had recently been completed. Test boards with different design details for CAF and surface insulation resistance (SIR) monitoring had been aged at 1000V DC, with hole-to-hole distances in the range 550 to 2100 microns for CAF and pad-to-pad distances of 440 to 1950 microns for SIR. All the CAF patterns had failed within 2,000 hours but there had been no SIR failures for the three no-clean solder pastes tested. The time to failure for CAF was inversely related to DC voltage. NPL had proposed a multi-partner project for investigating CAF failure, and IPC had organised a round robin on the prevention of SIR failures in CAF testing.

Electrochemical impedance spectroscopy had been utilised for rapid materials evaluation. This used AC impedance to determine the impact of flux residues, as an alternative to traditional DC SIR measurement. It was expected that its predictive capability could be developed into a non-destructive test method.

Wickham also briefly discussed developments in fast turnaround insulation resistance testing in damp environments, platen condensation testing, immersion testing and rapid in-process conformal coating evaluation, as well as a new measurement facility and test vehicles for the quick assessment of reliability of coatings under harsh conditions. Industry collaborators were invited to join a multi-partner project to evaluate electronic materials for harsh environments.




Emma Hudson Technical Consultancy

Solder Limits

The final presentation, forewarning the industry of imminent changes in UL solder limits, came from ICT Chair Emma Hudson. Urging material suppliers and PCB fabricators to get prepared without delay, she explained that solder limits were key parameters for UL Recognized PCBs, representing the soldering processes to which the PCB would be exposed during assembly operations and capturing all time spent over the maximum operating temperature and the maximum temperature reached. They were employed in many of the test procedures used to characterise a PCB as part of the recognition process.

Hudson stressed that if solder limits were exceeded during PCB assembly, the safety evaluation conducted on that PCB was invalidated.

Reviewing current status, she explained that the new editions of standards UL 796 for printed wiring boards, UL 796F for flexible circuits, UL 746E for laminates and coatings, and UL 746F for flexible materials, recently published, had all included standardised solder limits and assembly solder process requirements. These defined all the time spent over the maximum operating temperature, or 100°C whichever was greater, and the maximum temperature reached as measured on the surface of the PCB. The standards now included a new default solder process condition: six cycles of the IPC T260 profile.

UL had issued a bulletin to all manufacturers with PCBs Recognized under UL 796 and UL 796F explaining the concept of standardised reflow profiles, the updates to the standards and how they would be implemented.

UL Follow-Up Services would verify at the assembly company that any board certified from January 1, 2022 had suitable solder limits and assembly solder process parameters for the actual process, and if any PCB was not Recognized with the appropriate parameter it would be deemed a non-conformance.

Any changes or modifications to existing PCB types, including the addition of new materials, conductor parameters, solder limits, maximum operating temperatures and flammability rating made from January 1, 2022 would also be subject to the new inspection criteria. Existing board types that remained unchanged could be left as they were.

Hudson highlighted the need for laminate and solder resist manufactures to update their materials to the new solder limits and assembly solder process parameters, preferably to the default of six cycles of the T260 profile, otherwise the PCB manufacturers would face much more testing. 

She advised PCB manufacturers to talk to their laminate suppliers without delay about their plans to upgrade their material Recognition. Some testing would still be needed to upgrade PCBs to the new assembly solder process solder limits but if materials had the new values the amount of testing could be reduced. Similarly, solder resist suppliers could adopt the default assembly solder process parameters and their associated flammability testing requirements.

She suggested that PCB manufacturers who had impending changes to existing PCB types should consider the creation of duplicate types in their UL files, making copies that could then be updated as and when necessary, depending on the ease of maintaining the PCB type designation with their customer.

Her closing words were: “Be prepared as a PCB manufacturer. This is happening. Ask your material suppliers what they are doing to help you.”


The Institute of Circuit Technology Autumn Seminar 2021 was a great success. It provided an excellent technical programme and much more. It was a gathering of real people and a long-awaited networking opportunity.

Pete Starkey

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Section 7

bill wilkie

Bill Wilkie
Technical Director and Membership Secretary, Institute of Circuit Technology

Directors Report

Bill Wilkie, ICT

We are holding our Annual Foundation Course as a live event this year at Chester University with the first day at Merlin pcb, Deeside to be able to enjoy a facility tour in the afternoon. The Halls of Residence are not available this year, due to covid restrictions, so we have arranged accommodation at a local hotel, within easy reach of the campus. Read more....

Our Annual Symposium will also be live at the National Motor Museum at Gaydon with Happy Holden delivering the Keynote. Read more....


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Section 8

Industry News


We recently received a communication from DEFRA via the HSE regarding downstream user duties under UK REACH. It is very relevant for ICT member companies.

Important news regarding "Reach" Article 33 – Duty to disclose information about SVHC conatained in manufactured items.

The Department for Environment, Food and Rural Affairs (DEFRA) has launched a survey via the HSE e-Bulletin service in order to:
a) Assess the levels of awareness of the duties under Article 33, and
b) Understand businesses’ practical experience of implementing and complying with these duties.

Article 33 states that:
1. A manufacturer / supplier of an article containing a SVHC must disclose information about any SVHCs contained to the recipient. This duty applies all the way down the supply chain to the retailer of the manufactured item.
2. The retailer of the article must supply this information to the public within 45 days of a request from any consumer.

DEFRA states that previous research conducted in the EU found that levels of awareness are low and that there are difficulties in implementation. This disclosure duty has been a statutory legal duty since 2009, but many manufacturers and suppliers are not aware of it. The duty still applies to all UK manufacturers, suppliers and retailers after Brexit.

The communication from DEFRA confirms that “The Secretary of State for the Environment, Food and Rural Affairs is required to review Article 33 to assess its practical operation and whether or not to extend the scope beyond SVHCs to cover other dangerous substances such as skin sensitisers.”

ParaChem’s online compliance tool “ReachWARE®” has been updated after Brexit to cover the requirements of the new UK REACH and allows users to fulfil all disclosure duties under EU REACH and UK REACH. It will also include skin sensitisers if the scope is extended as
described above.

ReachWARE® is an online database for manufacturers (“downstream users” of chemicals) that have a legal duty to make disclosure reports under “The REACH etc. (Amendment etc) (EU Exit) Regulations 2019” (UK REACH)”.

It also facilitates compliance with;

EU REACH Reporting Duties
ROHS3 Reporting Duties

What’s the deal?

Any ICT corporate or individual member can subscribe to ReachWARE® for a reduced monthly fee. The subscription is normally £60+VAT per month, and this will be reduced to £45+VAT per month for twelve months for ICT members taking out a subscription in April 2022. Furthermore the £199+VAT set-up fee will be waived throughout April 2022.

There is no tie-in period and you can terminate your subscription at any time.

How do I sign up?

You can see information about ReachWARE® on our website before subscribing. There are downloadable guides to help with all aspects of using ReachWARE®.

Go to our website parachem.co.uk and register your interest. All enquiries received on or before 30th April 2022 will qualify for the discounts described above.

Atotech Atotech took part in IPC APEX EXPO 2022 and presented four technical papers this year, touching on the following hot industry topics “crystal structures in plated microvias”, “electroless palladium plating”, “Pd-free activation for electroless Cu”, and “nano structuring photoresist adhesion promoter”. Read more....
CCI Eurolam Christian Winkler – New colleague in Technical Sales
CCI is growing and our sales department is being further expanded. We are pleased to announce that Christian Winkler will be supporting us with his knowledge and experience as of 1 February 2022. Read more....

Lyncolec Rebranded as Special Products Division of Eurotech.
Poole based Lyncolec is being rebranded as Eurotech Special Products with effect from January 2022. The factory manufactures Flex, Flex Rigid and other specialist PCB products and has been part of the Eurotech Group since December 2019. Read more....

Merlin Circuit Technology Merlin Circuit Technology goes fully digital.
The printed circuit board industry has always relied on photographic and mechanical disciplines in the manufacturing processes to derive circuit images, solder mask apertures and legend notations for the components. Expensive photo plotting machines have been produced with high-definition films to create super accurate photo tools, however, this process carries… Read more
Merlin Flex

Merlin Flex, a global supplier of Flex & Flex/Rigid interconnect solutions, has been on the SC21 journey for over 10 years and after several years of continuously achieving the Bronze award, the company is pleased to announce it has achieved the Silver award status. Read more....

Teledyne Labtech Teledyne Labtech Announces New Advanced Graphite Embedding Capability for PCB Thermal Management.

New innovation provides weight savings for applications where size, weight and power (SWaP) are key. - Teledyne Labtech announces a major new capability allowing the embedding of layers of synthetic graphite within RF and microwave printed circuit boards (PCBs). Heat
management is a significant concern in many aerospace defense and space applications where size, weight and power (SWaP) are key attributes. Gallium nitride (GaN) solid state power amplifiers (SSPAs) are examples of increasingly common devices that benefit from careful heat management. This new technique allows efficient conduction of heat away from such devices, saving system weight and increasing their lifetime. Read more....
 Ventec Ventec announced that the asset purchase agreement with Holders Technology (AIM: HDT) in Europe was completed on October 21, 2021. The transaction completes Ventec’s acquisition of a range of PCB assets owned by Holders Technology’s German & UK operating subsidiaries. Read more....

Zot Printed Circuits are pleased to announce that they have placed an order for a new Schmoll MDI - supplied and installed by Schmoll Maschinen GmbH. The new digital imaging system increases capability and capacity for processing high technology, high reliability Printed Circuits. Read more....

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Section 9

Membership News 

bill wilkie

Bill Wilkie
Technical Director and Membership Secretary, Institute of Circuit Technology

members graphThere are currently 382 members of The ICT spread across the categories shown in the chart




NEW MEMBERS SUMMARY October 2021- March 2022

Membership No Name Company
Hon Fellows - The following past chairs of the Institute have been awarded Honorary Fellowship in recognition of their exceptional contribution to The ICT.
583 Steve Payne iNEMA
1036 Chris Wall Electra
2002 Martin Goosey MTG Research
10026 Andy Cobley Coventry University
10551 Gordon Falconer Zot Engineering
10552 Janine Schwestka  RUAG Space
10553 Jeff Cox  C-T Machinery
10022 - Fellow Chris Hunt Gen3 Systems
10172 - Fellow Steve Driver Jiva Materials
    Go back to Contents


 Section 10

Corporate Members of the ICT

Adeon Technologies BV adeon corp www.adeon.nl
Amphenol Invotec Ltd invotec corp amphenol-invotec.com
Atotech UK Ltd. atotech corp www.atotech.com
CCE Europe cce corp www.ccee.co.uk
CCI Eurolam cci eurolam corp  www.ccieurolam.com/en/
Electra Polymers Ltd electra corp www.electrapolymers.com
The Eurotech Group  eurotech corp www.eurotech-group.co.uk
Exception PCB Solutions  exception corp www.exceptionpcb.com/ 
Faraday Printed Circuits Ltd faraday corp www.faraday-circuits.co.uk
Flexible Technology Ltd flex tech corp  www.flexibletechnology.com/
Graphic plc graphic corp www.graphic.plc.uk 
GSPK (TCL Group) gspk corp www.gspkcircuits.ltd.uk 
HMGCC hmgcc corp www.hmgcc.gov.uk
Holders Technology UK holders tech2 corp ww2.holderstechnology.com
Merlin Circuit Technology Ltd merlin corp www.merlinpcbgroup.com
Merlin Flex Ltd merlin corp  www.merlinpcbgroup.com
Minnitron Ltd minitron corp www.minnitron.co.uk
Newbury Electronics Ltd newbury corp  www.newburyelectronics.co.uk
Photomechanical Services photomech corp  www.creekviewelectronics.co.uk
PMD pmd corp www.pmdchemicals
Stevenage Circuits Ltd stevenage corp www.stevenagecircuits.co.uk 
Teledyne Labtech teleydyne corp www.teledynelabtech.com
Trackwise Designs Ltd trackwise corp  www.trackwise.co.uk
Ventec Europe ventec corp www.ventec-europe.com
Zot Engineering Ltd zot corp www.zot.co.uk 
     Go back to Contents


Section 11

ICT Council Members

Council Members

Emma Hudson (Chair), Andy Cobley (Past Chairman), Steve Payne (Hon Deputy Chairman), Chris Wall (Treasurer), William Wilkie (Technical Director, Hon Sec, Membership & Events), Richard Wood-Roe (Web Site), Lynn Houghton (Hon Editor), Jim Francey,  Martin Goosey, Lawson Lightfoot, Peter Starkey, Francesca Stern and Bob Willis, 

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Section 12

Editors Notes

The ICT Journal

Lynn Houghton

Lynn Houghton
Journal Editor

Instructions / Hints for Contributors

1. As it is a digital format the length is not an issue. Short is better than none at all!

2. Article can be a paper or a text version of a seminar or company presentation. Please include data tables, graphs, or powerpoint slides. We can shrink them down to about quarter of a page. Obviously not just bullet points to speak from.

3. Photo's are welcome.

4. We would not need  source cross references

5. Title of presentation - Of course! Date, Job title of Author and Company represented.

6. An introductory summary of about 150 words would give the reader a flavour of what it's all about.

7. Style - we don't want out and out advertising but we do recognise that the author has a specialism in the product or process that will include some trade promotion. Sometimes it will be a unique process or equipment so trade specific must be allowed.

8. Date and any info relating to where or if this article may have been published before.

9. We can accept virtually any format. Word, Powerpoint, publisher, PDF or Open Office equivalents. 

10. Also, to make it easy, the author can provide a word file to go along with his original powerpoint presentation and I/we can merge it together and select the required images. 

11. A photo of author or collaborators.


I really do look forward to receiving articles for publication.

Lynn Houghton

This email address is being protected from spambots. You need JavaScript enabled to view it.

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