The Journal of The Institute of Circuit Technology

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The Journal of
The  Institute of Circuit Technology
Vol 16 No 2
April 2023

Links to Contents 

  Author  Section
Editors Introduction Richard Wood-Roe 
Calendar of Events Bill Wilkie  2
Practical Aspects of Selective Etching for High Density Interconnect Don Ball 3
Thermal Management in High Performance RF and Microwave PCB's John Priday 
Two-Layer Solder Resist Film for High Reliability Ying Hsuan Chou  5
Treatment of Polymeric Films Used for Printed Electronic Circuits Using Non-Thermal Plasma Radu Burlica 
Automation & the Journey to Your Smart Factory – Video Gallery Happy Holden 7
ICT Seminar and AGM 7th March 2023 Pete Starkey  8
Members News:  9
Industry News:  10
Membership Update:  New Members and Grading  11
Corporate Members


Council Members 13
Editors Notes Richard Wood-Roe 14


Section 1 Editors Introduction

rick profile2

Richard Wood-Roe
Journal Editor

In this issue of The Journal we have included a paper from Don Ball of Chemcut, explaining the practical aspects of etching copper for HDI applications. There is an absorbing overview of thermal management in high performance RF and microwave pcb's from John Priday of Teledyne. There is a paper describing a novel 2-layer solder mask for extreme applications from Ying Hsuan Chou of Taiyo. We also have an unusual paper from Radu Burlica, from Romania, on ambient plasma treatment for adhesion promotion for use in printed electronics.

We now have a video gallery of Happy Holden's valuable contribution to our series of Technical Webinars. This can be accessed from section 7 of this journal as well as links on our website.

In section 9 we give details of our members who have been awarded Honorary Fellow gradings for their contribution to the PCB industry.

I am grateful to Pete Starkey for his write up of the recent ICT AGM and evening seminar that was held in Meriden, West Midlands. 

Finally the industry news section highlights the activity of some of our Corporate Members.

  Go back to Contents


Section 2 Calendar of Events 

bill wilkie

Bill Wilkie
Technical Director and Membership Secretary



March 7th ICT AGM and Spring Seminar at Meriden. 

Council Meeting – Starts at 12 noon, Fab Group Meeting starts at 14:30, AGM/Seminar starts at 18:00 – to be followed by a buffet.

Manor Hotel Room Rate - £100/night B&B at ICT Rates

April 24-27th Annual Foundation Course, Chester
It is Annual Foundation Course time again and we are now in the 43rd year of this venerable Institution. Only three people have ever been in charge of the course, Geoff Paterson, who was the Technical Manager of Bepi Electronics and a Course founder, Lawson Lightfoot and Bill Wilkie. Details of this years' course can be found here. Read more...
June 6th  ICT Annual Symposium at the National Motorcycle Museum at the NCC, Birmingham
    Go back to Contents


Section 3

Practical Aspects of Selective Etching for High Density Interconnect
Don Ball
Chemcut Corporation

Editors Note: This paper is a few years old now. It has been included as it is still very relevant to today's manufacturing challenges.

 D Ball

Don Ball

1. Introduction

The fully subtractive etching process is still the most economical and fastest way to produce large numbers of printed circuit boards but it has its limitations.

First and foremost is the fact that the etch process etches sideways as well as down at a ratio of an approximately 1 unit increase in the width of a space to every 3 or 4 units down, depending on the etchant and etching conditions. This means there is a limit to the thickness of the copper foil in relation to the widths of the lines and spaces for HDI. Presently the practical limits for lines and spaces are 75µm (3 mil) lines and spaces in 35µm (1 oz.) foil, 50µm (2 mil) lines and spaces in 18µm (1/2 oz.) foil and 25µm (1 mil) lines and spaces in 9µm (1/4 oz.) or 5µm (1/8 oz.) foil.

So far the seemingly insatiable demand for smaller, lighter electronic devices with more and more capabilities built in have been met, in part, by decreasing the size of the lines and spaces on the interconnect boards and using thinner foils to accommodate the narrower lines and spaces.

However, thinner foils also limit the amount of amperage that can go through those high density interconnects. In the past year or so we have begun to get requests to look at the feasibility for the near future of production based on 50µm lines and spaces in 35µm foil and 25µm lines and spaces in 18µm foil using 30µm (1.2 mil) dry film.

This initiated some internal tests and it is the results of these tests, which include some insights on what the problems with HDI etching really are, some proposed solutions for these problems, and tests of the proposed solutions, that are presented here. The conclusion reached is that the proposed objectives are possible but attaining them, especially in a production environment, will be extremely difficult.

2. Preliminary Etch Tests and a Clearer Understanding of the Problems Involved

Since almost all of our testing in the last several years have been based on the practical limitations expressed above the obvious first step was to run some etch tests with 50µm lines and spaces in 35µm foil and 25µm lines and spaces in 18µm foil to see exactly what we were up against.

2.1 Test Patterns – For testing the 25µm lines and spaces a Conductor Analysis Technology (CATs) 1,1,1 multi-­‐pitch test pattern was used.

Figure 1 on the next page shows the layout of one of the test patterns. Each pattern is about one inch square (2.54 cm) and there are 352 of these patterns in a 22x16 grid on a 24” x 18” inch (601mm x 457mm) panel. The multi-­‐pitch designation means there are four different line and space combinations within each test pattern. The 1,1,1 means this pattern starts with a 1 mil line and space on the innermost pad and line and space widths increase by one for each subsequent pad up to 4 mils. Therefore we have a 1 mil line, 1 mil space, 2 mil line, 2 mil space, etc. There is a 1.5 mil (37µm) space between the two 25 µm lines where they run side-­‐by-­‐side.

For testing the 50µm lines and spaces on 35µm foil a CATs 2,2,1 multi-­‐pitch pattern was used. This is essentially the same layout but starting with a 2 mil line and space increasing in steps of one mil to a 5 mil line. Where the 2 mil lines run side-­‐by-­‐side the space between them is 2.5 mils (63.5µm).

2.2 Foil Considerations – Reverse Treat Foil was used for these tests for two reasons. First, with the rough side profile facing up, it maximizes the surface area for the dry film to adhere to, an important consideration when the finished line width is likely to be only 12µm or less across the top of the line. Second, with the smooth side laminated to the fiberglass substrate there is less copper imbedded in the epoxy to remove and a slightly decreased etch time.

fig 1

Figure 1 – CATs Test Pattern

Etchant Chemistry and Considerations – Cupric chloride is the first choice for etching copper because, with regeneration, it maintains a constant etch rate and generates the least amount of etchant to have to eventually dispose of. Ferric chloride gives a little less undercut and slightly better etch factors when used to etch copper but, when used with copper, it can’t be regenerated so the cost of new etchant and the cost of disposal of the old etchant far outweighs the slight etch quality advantage.

Undercut and etch factor have been a concern for many years and we have done extensive testing in the past on different chemistry parameters to minimize undercut and maximize etch factors (to be covered in a little more detail in the next section).

The most important factors for cupric chloride etching are specific gravity and free acid content with higher specific gravities and lower free acid contents giving noticeably better results for both undercut and etch factors. The cupric chloride for the tests was run at a specific gravity of 1.330 (36o Be) and a free acid level of 0.8N (29.2 gpl).

2.3 Preliminary Etch Test Results and Analysis – The test panels were cleaned and laminated with Dupont FX 930 dry film paying special attention to the lamination parameters to be sure that pressures, lamination roll temperatures and exit temperatures were all within the recommended ranges. The exposure unit was a Tamarack 161B and the major parameter here for HDI was a full one minute drawdown time on the vacuum to be sure of the most intimate contact possible between the photo tool emulsion side and the surface of the protective coating on the dry film. The panels were developed and checked to see that the narrowest spaces were cleaned out and then etched and stripped.

The results of the 50µm lines and spaces on 35µm copper were encouraging with over 80% yields for the 50µm lines in terms of opens and shorts. This is not great but certainly much higher than expected. The major problem was a very tight window for conveyor speed between over and under etching.

It was hoped that similar results could be obtained with the 25µm lines and spaces in the 18µm micron foil since everything was cut by half except for the thickness of the resist. Such was not the case, however, as the test patterns displayed a 100% failure rate due to opens when etched long enough to clean out the 25µm spaces so there were no shorts. The good news was that none of the opens were caused by resist adhesion failures even though the widths at the tops of the lines were as low as 8.2µm (0.33 mils). There were two places where there were always opens. The first were the isolated 25µm lines leading to the pads, which are easy enough to fix with some artwork compensation. The other place was where the 25µm lines took a 90o turn. This was a little puzzling until a little simple geometry was applied as shown in Figure 2 below. Where the 25µm space makes a right angle turn the hypotenuse of the right triangle formed is 35.8µm, giving the etchant a little more space to work in, resulting in a little faster etch rate at this point. By the time the 25µm spaces to either side are etched clean the line at the corner has etched through.

fig 2

 Figure 2 

Figure 3 illustrates a little more clearly the difference in etch speed in a 36 to 37µm space as opposed to a 25µm space. This is a cross section showing the 37µm space between adjacent 25µm lines and the 25µm spaces between the adjacent 25µm and 50µm lines after etching. It is quite evident that the 37µm space is nicely cleaned out before the bottom of the 25µm space has even been reached.

fig 3
 Figure 3

2.4 Etch Rate and Etch Factor vs. Developed Space – Intellectually it is known that, as the space between lines decreases, the time needed to etch them out increases. It was clear after these initial etch tests that the rate of drop off in etch rate was much greater than we anticipated.

A simple test was devised to quantify the change in etch rate with decreasing spaces. A test pattern was prepared with 15, 12.5, 10, 7.5, 5, 4, 3, 2 and 1 mil spaces (381, 317, 254, 191, 127, 102, 76, 51 and 25m). The patterns were etched for one minute in cupric chloride and cross sectioned. Measurements were taken of etch depth and etched width across the top of the space. The etch rates were calculated as were the etch factor. In this case the etch factor is the ratio of the increase in width of one side of the space to the depth of etch expressed as a percentage. A higher percentage generally means more undercut (less undercut is more desirable).

Figure 4 is a chart showing the results of these tests. The solid line and the left axis are the etch rates and the dashed line and right hand axis are the undercut percentages. These tests were done with a 15µm dry film.

fig 4

 Figure 4

As can be seen, the etch rates in the spaces remains constant until the space gets to 5 mils (125µm). There is a small decrease between 4 and 5 mils (100 and 125µm), a little more decrease between 3 and 4 mils (75 and 100µm) then a large drop off between 2 and 3 mils (50 and 75µm) and an even larger relative drop off between 1 and 2 mil (25 and 50µm) spaces. The fall off in etch rate between the 2 mil (50µm) spaces and 5 mil (125µm) spaces is 17% and the fall off between the 1 mil (25µm) spaces and 5 mil spaces is almost 42%. The difference in etch rates between the 2 mil and 1 mil spaces is almost 30% by itself.

It can also be seen that the etch factor percentage also increases as the spaces decrease. This is a little misleading, as the actual increase in the widths of the etched spaces remained fairly constant over the range of spaces in this test; the ratios went up because there was less etch depth in the same amount of time.

The best explanation, without getting into such things as fluid viscosity, grain boundary attacks and diffusion layers, for the above phenomena is probably the easiest one. As the depth to be penetrated by the etchant (resist thickness plus foil thickness) increases in relation to the width of the opening available for the etchant to get into, the difficulty of getting fresh etchant to the copper surface and spent etchant away from the copper surface increases and the slowdown in the exchange rate slows the rate of etch. In addition, the above chart shows that the slowdown in etch rate is not linear but exponential.

It should also be noted that the fall off in etch rate will be sharper for a thicker resist than the 15µm dry film used in this test and a little shallower for a thinner resist but still substantial. At this point it is possible to get bogged down in all kinds of theoretical explanations and mathematical calculations. Since the title of the paper is Practical Aspects of HDI Etching it is time to back off and determine what we have learned from the above testing.

2.5 Conclusions after Preliminary Etch Tests
50µm lines and spaces can be done in 35µm foil though it is difficult. 25µm lines and spaces in 18µm foil are almost, but not quite, possible at present. Further testing was done using 25µm lines and spaces in 18µm foil with 30µm dry film since anything learned here will also be applicable to other resist and space width combinations.

The etch rate slows down dramatically in the 25µm spaces to the point that any 25µm line that is bounded by a 37µm space or more will etch out before the 25µm spaces are fully cleaned out.

Some of the above problems can be resolved by careful artwork design but, from an equipment suppliers view, it would also be beneficial to find a way to increase downward etch without increasing sideways etch. In other words find a way to increase the etch factor.

3. Attempting to Improve Etch Factor and Reduce Undercut

3.1 Summary of Past Explorations – Etch factors and undercuts have been important considerations for both the printed circuit and photo chemical machining industries for many years. There have been many investigations into these areas in the past that have affected the approach taken here for HDI. Following is a brief summary of past tests and conclusions. (For those who would like more detail on the test methods and data used to reach these conclusions go to our website at, click on Technical Info and download “Thoughts on Undercut”).

3.2 Nozzle Type – One of the first things that always comes up in any discussion on etch factors and undercut is whether fan nozzles or cone nozzles are better and the debate sometimes can get quite passionate. However, the data from extensive testing shows there is very little, if any, difference in the undercut characteristics of fan or cone nozzles.

3.3 Nozzle Flow Rate/Droplet Size – This is the second thing that comes up most often in the etch factor/ undercut improvement discussions. In the world of spray nozzles the droplet size is directly related to the flow rate so lower flow rate nozzles have smaller openings and thus smaller droplets. The thinking goes that if you have narrower opening to get the etchant into then a smaller droplet size will be better at penetrating into that opening. The truth is that even the lowest flow rate nozzles practical to use in a spray etcher still have droplet sizes in 400+µm range, still far larger than a 25µm space. In any case, the droplets do not impact directly on the space anyway. They impact on the static diffusion layer on the surface of the copper (yes, even on the bottom side). The ability to get fresh etchant to the copper surface is directly dependant on the force with which the droplet strikes this surface but a droplet with half the radius has eight time less mass than the larger droplet and the etch rate falls off. In the end you wind up with the same etch factor and a slower etch rate.

3.4 Nozzle Distance from Work – Moving the nozzles closer to the work means the force of the spray is increased thus improving the efficiency of the exchange of etchant in the narrow spaces. This is also the source of some of the fans versus cones controversy. Testing has shown that undercut performance does indeed improve for cone nozzles as they get closer to the surface but for fan nozzles the undercut improves as they get farther from the work surface. Thus, replacing fan nozzles with cone nozzles in equipment designed for fan nozzles showed a loss in undercut performance and vice versa. Also, moving the nozzles closer to the work means more nozzles are needed for complete coverage, meaning more solution on the surface, which in turn negates some of the advantage of the increased force. In short, there was a small improvement in undercut performance but nothing to get excited about.

3.5 Spray Pressure – Testing showed very little improvement in undercut with increasing spray pressure from 20 to 80 psi (1.4 to 5.4 bar). The increase in fluid flow negates the benefits of the higher droplet velocity.

3.6 Etchant Temperature – No significant difference in undercut performance was found from 100o to 160oF (38o to 71oC).

3.7 Cupric Chloride Specific Gravity and Free Acid Level – As noted in the beginning of this paper specific gravity and free acid levels were the only things that lead to noticeable improvements in undercut performance. It should be noted that the improvements were incremental and not drastic but at least measurable. Higher specific gravities drastically reduced etch rates without improving undercuts while lower acid levels actually led to undercut performance getting worse.

3.8 Revisiting Some of the Above Parameters
The data for the above tests was gathered during tests for a company making lead frames which were etched through from both sides in 150µm (6 mil) copper with fairly large developed openings in the resist. Also, this was rolled, annealed copper, which has slightly different etch characteristics than electroplated copper. It was felt that in the case of 25µm spaces in electroplated 18µm foil it might be worthwhile to retest some of the above parameters. So the effects of nozzle type (this debate never really ends, no matter what the data says), etch temperature and spray pressure were revisited.

These tests were basically a repeat of the tests done to determine the etch rates for the various widths of developed spaces. A one minute etch followed by cross sectioning and measurements of etch depth and final etched width across the top. Tests were conducted from the bottom side to avoid complications introduced by topside etchant puddling. The tables below show the results for each test.


fig 5

 Figure 5 -­ Comparison of Cone and Fan Nozzles

 The fan nozzles etched a little slower than the cone nozzles under equal conditions but the etch factors were virtually identical, confirming that nozzle type has little to do with final undercut.


fig 6

Figure 6 - Etch Factor Comparison for Etchant Temperatures of 38o C and 54o C

 As expected the etch rate was slower for the lower temperature but the etch factors were the same in the end. The equipment used in this test was made of PVC so the maximum temperature allowed was 54o C. However, there is nothing in past testing that suggests that any higher etch temperatures would change anything other than etch rate.


fig 7

Figure 7 - Etch Factor Comparison for 25µm Space at Different Spray Pressures

This also confirms results obtained in earlier testing. Once the spray pressure gets above 20 psi the etch factors remain constant, the only change being etch rate.

At this point we have only confirmed that the test results obtained in the early 1990’s when working to reduce undercut in high pin count lead frames. There were many other equipment and chemistry parameters tested than those covered here but those that showed improvement in etch factor (optimum placement of spray nozzles, reduction in topside etchant puddling) were incremental improvements rather than huge revelations and most of those have already been designed into the new generation of equipment beginning in the early 2000’s. Unfortunately, some of the most obvious things that one might think of to improve etch factor (different nozzles, smaller droplet sizes, higher spray pressures) have been confirmed as ineffective.

One complicating factor in all these tests was that, no matter what changes we made, the spray was not impinging directly on the copper surface. On the topside there is always an etchant puddle that the spray impacts upon while on the bottom side the spray has to deal with the conveyor rods and wheels which scatters and reduces the velocity of the droplets. The bottom side situation is made even worse by the fact that most HDI is done on thin or flexible substrates, which require more wheels than normal for support. This complicating factor might have disguised any improvements in etch factor that may have occurred in the previous tests.

A quick screening test was set up where the conveyor rods containing any wheels that masked the lower spray nozzles were removed giving the nozzles a clear shot at the copper surface without an etchant puddle or masking objects. Tests were run with cone and fan nozzles at several different spray pressures. The results reconfirmed that there is no inherent advantage of one type of nozzle over the other and different pressures changed the etch rate in the fine spaces (as well as that in all the other spaces) but had little, if any, effect on etch factor. Changing the etch speed without changing the etch factor just produces bad test patterns faster.

Unfortunately, all the other tests that dealt with equipment modifications to improve etch factor produced the same results, the etch speed could be changed but the etch factor remained the same.

Quite frankly, at this point there is very little that can be done to the equipment design that is going to improve undercut without some radical redesign to test some other concepts, but even this is no guarantee of success. So, is there anything else that might be done to improve the situation? An old saw from the days when HDI meant going from 200µm lines and spaces to 100µm lines and spaces says “Under expose and over develop for fine lines”. The question is whether there was and still is any truth to this bit of sage’s wisdom especially considering the considerable improvements in dry film since those years. A screening test was set up to see if this concept was worth following through.

4.1 Dry Film Exposure Tests – The recommended exposure for the dry film used in these tests was step 6 to step 8 on a 21 step density tablet. On the 5000 watt exposure unit used this translated to a 4.9 second exposure time for a step 6 and a 5.5 second exposure time for a step 7. All the previous tests were done using the 5.5 second exposure time. Six test panels were prepared and exposed at times of 5.5, 5.3, 5.1, 4.9, 4.7 and 4.5 seconds respectively. The panels were developed and etched together and the tops and bottoms of the 25µm lines and 75µm lines were measured for comparison. There was not much improvement until the 4.9 second exposure was reached and the resist exposed at 4.7 and 4.5 seconds had adhesion problems. The results for the 5.5 second and 4.9 second exposures are shown below in the table and cross sections.

fig 8

 Figure 8 – Line Width Measurements


fig 9

 Figure 9 – Cross Sections - 5.5 second exposure 4.9 second exposure

 The results above show that, under the same developing and etching conditions, the 25µm space has etched out more completely for the 4.9 second exposure. More importantly, while the 25µm line is obviously etched more, the dimensions of the 75µm line did not change all that much demonstrating that a lower exposure level may actually help clean out the 25µm spaces faster in relation to the wider spaces. The etch factor for 25µm line did not improve that much but the etching was definitely better.

It was hoped that, at the time this paper was solicited, that a full set of tests to confirm these results would be completed by the time the paper was due but other duties have intervened and they have not yet been started. However, the preliminary tests shown here do show that this line of inquiry is worth pursuing.

4.2 Developing Time Tests – Another preliminary test was run with the 4.9 second exposure to compare developing at a conveyor speed set for a 60% breakpoint, as used on the above exposure tests, with a speed set for a 40% breakpoint. Visually, the results seem to show a further slight improvement in the clean out of the 25µm space in relation to the wider spaces. Again, the full set of tests to confirm this conclusion has yet to be completed but the outlook is hopeful.

4.3 Tests for the Near Future – Others have indicated that replacing the free hydrochloric acid by saturating the cupric chloride with sodium chloride, table salt, greatly improves etch factors. This is on the list to be done as soon as possible. Also, there have been developments in spray nozzles and chemical additives for cupric chloride. Samples of both of these will be available by the time this paper is delivered and are also high on the priority list for immediate testing as time allows.

5. Practical Aspects for HDI Etching That Have Been Learned During the Course of These Tests

The original impetus for this investigation was a request to look into the feasibility of etching 50µm lines and spaces in 35µm foil and 25µm lines and spaces in 18µm foil while using a 30µm dry film. This has to be the ultimate worst case scenario for HDI production but the initial trials clearly defined the problems faced, namely:

1) The etch rates in spaces less than 50µm fall off drastically when compared to wider spaces and

2) because of this, any place where a line of 25µm or less is bounded by a space greater than the line width will be etched out before any spaces the same width as the line can be cleaned out enough to prevent shorts.

The ultimate solution to the problems would be to find a way to increase the rate of downwards etch while not increasing the rate of sideways etch.

While this goal of increasing the downwards etch without increasing the sideways etch has not yet been attained there were many practical things learned in preparing and etching the test samples that could save a lot of time and effort for anyone engaged in HDI. These observations are listed below although not necessarily in order of importance.

5.1 The original task of etching 25µm lines and spaces in 18µm foil and 50µm lines and spaces in 35µm foil can be done but it won’t be easy, especially in a production situation. While I would like to be able to say that getting the latest, greatest new etching equipment will solve all your HDI problems this would be untrue. Every step in the production process will have to be looked at and improved.

5.2 There is very little that can be done, mechanically, to present etching spray machines that will improve the yields for HDI. The need is to increase downward etch rates without increasing sideways etch rates. Such things as different types of nozzles, smaller droplet size nozzles, increasing operating pressures and temperatures, removing obstacles to the spray, etc., either have no effect or just increase the overall etch rate without improving etch factor. At best there is no change, at worst they merely allow you to make scrap at a faster rate.

5.3 Experimenting with exposure times (less exposure time) and developing times (more developing time) seems to improve the overall etch rates in the narrowest spaces without affecting the etch rates in the wider spaces as much. This is definitely worth taking a look at.

5.4 The best way to improve HDI output may be a careful look at artwork design and creative compensation of the artwork at weak points. This may take the form of making sure the space between lines remains the same at right angle turns and shading the line width towards the side where a line is bounded by a wider space than the other side.

The above conclusions are a direct result of the testing done on HDI. The following conclusions are general observations made during the course of sample preparation and testing:

5.5 Soft contact exposure where the phototool is attached to the glass of the exposure frame and brought into contact with the resist at relatively low vacuum pressures of 4 to 6 psi may not be adequate for exposing sub 25µm lines and spaces even with a highly collimated light source. Harder contact and longer vacuum drawdown times have improved yields dramatically.

5.6 Lasers plotters used for imaging, either for exposure of the phototool or direct imaging of the resist, need to be looked at carefully for sub 25µm lines and spaces. The dot size used for lines perpendicular to the laser travel is of particular importance since the edge of the line must be as smooth as possible. Too coarse a dot size may result in added difficulties in cleaning out the space. Smaller dot sizes are better but can greatly elongate plotting time. Some experimentation should be done to find the optimum compromise.

5.7 The original request to explore the feasibility of using 30µm dry film for these HDI tests was basically economic. Thinner dry films are more expensive and even thinner liquid resists require capital investment for application and curing as well as time needed for a learning curve. The company originating the request was anticipating high production runs and was hoping to avoid adding cost to the product. While the conclusion based on testing is that it is possible to use a 30µm resist it may not be viable in a high production situation. A thinner resist will definitely make things easier. Experience shows that one should seriously consider a liquid or electro-phoretic resist that allows resist coatings of 5µm or less.

5.8 Finally, it can be extremely frustrating making adjustments to the etching equipment to get optimum results due to the extremely narrow working windows for conveyor speeds when etching lines and spaces below 50µm. While etching machines are made to exacting standards they are still hand built to order and each individual machine has its own quirks with sweet spots, cold spots and hot spots in different places. In the ordinary course of events these quirks are hardly noticeable but they can become important players in HDI. It is unlikely that any individual etcher is going to give even results on large format HDI panels without a lot of individual spray tube adjustments. To further complicate the situation, the nozzles used in spray etchers are mass produced using a moulding process. They must meet certain specifications as to flow rate, spray angles, etc. but these specifications are fairly broad. Again, in the ordinary course of events any variations in individual nozzles tend to be unnoticeable but when sub 50µm lines and spaces are involved a nozzle at one or the other end of the acceptance criteria can cause problems. Most etchers today allow adjustments to individual spray tube pressures, either automatically or manually, to even out differences in the spray pattern but if HDI is involved it may be necessary to track down and replace individual nozzles to get the best performance.

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Section 4

Thermal Management in High Performance RF and Microwave PCBs

John Priday CTO, Teledyne Labtech

 john priday

John Priday
CTO, Teledyne Labtech

As new RF and microwave systems evolve, we are seeing a greater need for effective thermal management and significantly higher RF performance from Printed Circuit Boards (PCB’s) and subsystems; at the same time these systems are required to decrease in mass and still offer greater functionality than ever before. Constraints like these are often most acute in applications where Size, Weight and Power (SWaP) are high priorities such as military and aerospace and typically include RF power amplifiers and phased array TxRx modules. This paper reviews the various methods of thermal management and reviews in detail the advantages of “Coin” technology versus traditional thermal via technology.

High density active power devices, such as GaN power transistors, can dissipate significant heat. One of many roles that the PCB has to perform is to channel heat from the underside of the semiconductor device through to the chosen heatsinking scheme as efficiently and effectively as possible. The design challenge is how best to accomplish this while achieving the other trade- offs required such as RF performance, manufacturability and cost.

Methods of Thermal Management
Traditionally, designers have simply added plated through holes (PTHs) to thermal/ground pads under components to take heat away through the circuit to a thermal sink such as a cold wall. Unless the assembly process includes a step to pre-fill these PTHs with solder there is a high risk that solder will be robbed from under the component into the holes leading
to a poor and potentially unreliable connection. Another solution often used is to have these PTHs under the components filled with a proprietary via plugging paste and plated over the top to give an uninterrupted ground pad. The plugging pastes typically used are electrically non-conductive and offer a relatively low thermal conductivity of around 0.6 W/mK compared to a conductivity of copper of 400 W/mK, so do not contribute much to the thermal transfer. Electrically and thermally conductive paste, for example silver (Ag) loaded epoxy, can be used to fill the thermal PTHs but even with Ag epoxy the thermal conductivity of these pastes is typically in the range of 4 to 30 W/ mK depending upon type - still very low. Figure 1 a) shows an example of a cross section though a filled and over- plated via. Figure 1 b) shows a typical application with filled thermal vias within the ground pad. If you look closely you will notice subtle outlines of the thermal vias in the central large ground pad.

To improve thermal conductivity one option is to increase the plated wall thickness of the PTHs from the standard 25um, to 100um for example. Often a greater number of smaller PTHs within a ground pad can provide a more effective thermal path than fewer larger PTHs.

fig 1a

Figure 1: a) Cross-section of filled via

Device Ground Pad
fig 1b

Figure 1: b) photo of typical device ground pad with over-plated vias just visible

  fig 2

Figure 2: Comparison of total thermal conductance of different filled vias

There are limits to the effectiveness of heat transfer using a traditional ground pad with PTHs. Figure 2 shows the results of calculations of four different cases, with detailed calculations shown in Appendix 1. Starting with a typical case of PTHs with 0.1mm thickness1 of wall plating, it examines the overall thermal conductance with vias filled with a non-conductive filler (Figure 2 a). Using this as the base case, it then examines increasing the number of vias (Figure 2 b), then changes the filling from non-conductive to conductive silver epoxy of two different thermal conductivities (Figure 2c and 2d). As can be seen the benefit of using Ag epoxy instead of standard non-conductive plug paste to fill the vias is limited and generally not worth the additional expense.

1 While a through-hole wall thickness of 0.025mm is standard in non-thermally challenged applications, we usually recommend 0.1mm where heat transfer is important. Note that if standard 0.025mm plating was used for case 2a, then thermal conductance would only be 0.96 W/°C. fig 3

Figure 3: Examples of the use of copper coins

For many leading edge applications the total thermal conductances shown on previous page are not up to the task. A more effective approach is to use copper coins that are integrated into the circuit’s structure. For ease of comparison, a simple approach is shown in (Figure 3 a), where a 6mm x 6mm square coin is modelled. A more frequently used approach is to have the coin stepped so that heat is not only efficiently conducted away but also spread. This is modelled in (Figure 3 b), and a cross sectional photograph of a real stepped copper coin shown in (Figure 3 c). The larger area of copper provides a larger surface area in contact with the cold wall, providing improved thermal transfer. More detailed calculations are given in Appendix 2.
fig 4

Figure 4: construction of metal-backed circuits

Ultimately metal backed circuits offer an ideal solution where large amounts of thermal energy need to be dissipated, as shown in Figure 4. The metal backing can be copper, aluminium or brass as this type of circuit is typically used for solid state power amplifiers (SSPA) and can be of either pre-bonded or post bonded structure. In the case of pre-bonded circuits this is where the substrate is supplied pre-bonded to a thick metal backer. This does limit tracking to a single layer and presents issues during processing as invariably machining operations have to take place after the circuit traces have been formed. Great care needs to be taken to avoid damaging critical circuit features. The advantage is that this provides an excellent ground plane reference.
fig 5

Figure 5: The assembly of post-bonded circuits

The post bonded alternative is easier to manufacture in so much as the circuit is produced and verified before being attached to a pre-machined and plated metal backer as shown in Figure 5. Post bonded circuits can have more than a single layer of conductors. Generally, the circuit is bonded to the metal backer using a conductive adhesive layer. For both pre and post bonded circuits the components that require heat to be transferred away are mounted directly onto the metal backer through openings within the circuit.
fig 6

Figure 6: Examples of metal-cored circuits

A more complex solution is metal-cored circuits. These can be usefully employed where space is limited and high isolation between RF and control is required in addition to thermal management. Heat being transferred from components to the core can either be through thermal vias or by direct contact through cavities within the circuit that the components are mounted on. Consideration must be given to removing heat from the core. Typically, circuit substrate is machined away from two edges to expose the core so it may be clamped within the chassis to transfer heat. In the case of thermal vias where holes are blind with diameters <0.2mm and depths <0.3mm the holes can be filled with copper using a blind hole plating process. Figure 6 shows examples.
fig 7

Figure 7: Machined copper plane with up-stands, applicable for small circuits

Another technique developed by Teledyne Labtech for thermal management on small circuits (<25cm2) and where the overall thickness is limited, yet several devices require thermal management is to employ a machined copper plane with up-stands (pillars). This provides an excellent thermal path way and the heat can be distributed efficiently through the thermal plane for transmission to a cold wall. An example is shown in Figure 7.

For very high power applications, metal backed circuits currently offer the best solution for high-power solid state RF devices that are flange mounted; they do not cater well for SMT components requiring thermal management. Where SMT components with high dissipation requirements are used, coins provide an effective solution for thermal management. If the required power dissipation is lower, thick walled filled vias offer a lower cost alternative to coins. Metal core and machined copper planes are generally only employed where space is limited and cost is not the overriding factor. There are thermally conductive substrates available for RF applications but even these generally have rather modest thermal conductivity of typically 1.0 to 1.5 W/mK

 app 1

Appendix 1 – Modelled PTHs
 app 2

Appendix 2 – Thermal Vias assuming non-conductive filler

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Section 5

 Two-Layer Solder Resist Film for High Reliability
Ying Hsuan Chou, Daichi Okamoto, Hidekazu Miyabe
Taiyo Ink Mfg. Co., Ltd.


Ying Hsuan Chou
Taiyo Ink Mfg. Co., Ltd.

In this paper, we reveal the development of a novel two-layer Solder Resist (SR) film which consists of a low Young's Modulus layer that possesses excellent adhesion to the substrate and a thermal resistance layer which is composed of resins with high thermal resistance and great toughness. This novel two-layer SR film exhibits superior resolution and crack resistance. Furthermore, the amount of warpage is extremely low. In general, materials with low Young's Modulus and high elongation exhibit weak cross-link density. This results in poor thermal resistance and delamination when assembling at high temperatures. Here, we can inhibit delamination successfully by this new two-layer structure film, with superior thermal resistance.

The Coefficient of Thermal Expansion (CTE) of conventional SR for Flip Chip-BGA is 35 ppm, and modulus is 4.5 GPa, whereas, this advanced two-layer SR film exhibits CTE of 66 ppm, and modulus of 2.3 GPa.

In order to compare the crack resistance between conventional SR and newly developed two-layer SR film, the film was laminated on BGA substrate (substrate size is 50 mm x 50 mm), patterned by photolithography and cured. A 25 mm x 25 mm chip was then mounted on the BGA substrate by flip-chip bonder. Conducting thermal cycle tests (TCT) and observing the number of cracks after 1000 cycles of TCT. The crack occurrence frequency of the conventional SR is 65%, whereas that of the new two-layer SR film is 4%. We proved clearly that high CTE and low Young's Modulus demonstrate overwhelmingly high crack resistance. Furthermore the high resolution of this newly developed two-layer film enabled the formation of SR opening (SRO) as small as 40 µm. From the above results, the newly developed two-layer SR film is beneficial for the next generation high-density package, especially for the outermost layer of FC-BGA packages and applications that require higher reliability.

Key words
two-layer solder resist film, low Young's Modulus, reliability, crack resistance, resolution, high-density substrate

Along with the growth of artificial intelligence (AI) technology, self-driving cars become more realistic. It is expected that the AI needs to have memory bandwidth of more than 1 TB per second to drive the car safely. To realize such high bandwidth, IC package needs to be denser1. Increased demands for higher density package substrates drive higher resolution and excellent reliability (outstanding crack resistance at thermal cycle test). The requirements for SR are getting more critical. In order to enhance crack resistance, the SR will have the characteristics of 1) low linear expansion, 2) low Young's Modulus, and 3) high elongation.

Conventionally, by lowering the thermal expansion rate of the SR, the amount of deformation caused from the difference of expansion rate between the substrate and SR can be reduced. When stress is decreased, then cracks can be suppressed. Unfortunately, to decrease linear expansion can increase the Young's Modulus. Therefore the reduction of stress is limited. In some cases, the materials characterised as low linear expansion still demonstrate insufficient crack resistance. This is attributed to the feature of high Young's Modulus. Thus, we assume that the property of low Young's Modulus is beneficial for crack resistance.

It is furthermore known that the material with low Young's Modulus is characterised by weak cross-link density, giving rise to inadequate thermal resistance. In this regard, we apply a thermal resistance layer which is composed of resins with high thermal resistance onto the low Young's Modulus material layer. Because of this advanced two-layer configuration, we can attain thermal resistance and crack resistance at the same time.

Moreover, in order to reach high resolution, the influence of inorganic fillers on resolution is also explored in our paper. Higher filler content of SR would be a major challenge of high resolution. High amounts of filler may cause higher UV light reflecting and scattering which affects lithographic resolution obviously2.

Briefly, the aim of our work is the development of a novel material with low Young's Modulus exhibiting superior performance, including crack resistance, resolution and extremely low warpage. Additionally, we come up with a unique two-layer configuration to overcome the weak thermal resistance, which is the major drawback of low Young's Modulus material.

1. The Evaluation of TCT Crack of Conventional SR
The crack resistance of SR is highly important especially for the Flip Chip BGA substrate. This is based on the current tendency towards enlarged chips, higher density and finer pitches.
Generally, to improve crack resistance, low CTE materials are utilized frequently. Here, we observe Young's Modulus, CTE and crack occurrence after the thermal cycle tests (TCT) for various conventional SR.
The test conditions of TCT are described below and a SEM image of crack after TCT is shown in Fig. 1.

  • SR thickness:20um
  • Pre-condition: 85ºC / 60% R.H. / 168 h (MSL2) + Reflow (285ºC, Air) x 3 times.
  • TCT condition: -65ºC (30 min.) ⇐ ⇒ 175ºC (30 min.) / 1000 cycle
  • Observation: Count the number of cracks at 160 points by optical microscope.

fig 1

Fig. 1. The SEM Image of Crack after TCT

Table 1 shows the results of Young's Modulus, CTE and crack occurrence frequency of conventional SR. The Young's Modulus and CTE are measured by tensile tester (Autograph AG-X (Shimadzu Corporation)) and
thermomechanical analysis (TMA-Q400EM (TA Instruments)), respectively. These results apparently reveal that a decrease of the CTE is accompanied by an increase the Young's Modulus, leading to the worse crack resistance.

Table 1. The Results of Young's Modulus, CTE and Crack Occurrence Frequency of Conventional SR

table 1


Furthermore, in order to understand precisely the correlation between Young's Modulus and crack occurrence frequency, we investigated the crack occurrence frequency of low Young's Modulus SR and compared the results to conventional SR. Fig. 2 exhibits the tendency that as the Young's Modulus becomes higher, the crack occurrence frequency of conventional SR increases significantly. In contrast, SR with 2~3 GPa Young's Modulus is exhibiting below 5% crack occurrence frequency. This result suggests that the material with low Young's Modulus can relieve stress and inhibit cracks from occurring. In our opinion, except for low CTE materials, low Young's Modulus materials also could demonstrate superb crack resistance.

fig 2

Fig. 2. The Correlation of Young's Modulus and Crack Occurrence Frequency of Conventional SR and Low Young's Modulus SR

2. The New Low Young's Modulus Material
We developed a new material with low Young's Modulus which is expected to have outstanding crack resistance. In principle, the cross-link density of material could have an effect on Young's Modulus. The low Young's Modulus is caused from low cross-link density, resulting in poor thermal/chemical resistance. This may lead to delamination during high temperature processes such as flip-chip bonding, reflow and so on.

It has been reported that, the high loading of inorganic filler in SR has contributed to excellent thermal resistance. Therefore to enhance thermal resistance, we introduced some fillers in the resin matrix and observed the crack occurrence frequency. Table 2 indicates that depending on the contents of filler, the CTE decreases from 70 to 41 ppm, and Young's Modulus increases from 1.3 to 3.0 GPa. In addition, the crack occurrence frequency is almost 0 % when the fillers loading is increased from 0 % to 45 %. In brief, this new low Young's Modulus material could reduce stress efficiently, thus, cracks can be suppressed perfectly.

Table 2. The Results of Young's Modulus, CTE and Crack Ratio of Low Young's Modulus Material

table 2

As we know, higher filler loading would be a major challenge of high resolution, because the large amounts of filler may cause UV light reflecting and scattering at the interface between the resin and fillers. We observed the resolution of this low Young's Modulus material and summarize in Table 3. It clearly indicates that higher filler ratio leads to higher light scatter during the UV exposure process and thus deteriorates resolution. In conclusion, this low Young's Modulus material possesses excellent crack resistance but shows deficiency in resolution when adding a large amount of filler. Consequently, in order to overcome the challenge of high resolution, we set out to eliminate all fillers.

Table 3. The Resolution of Different Filler Content in Low Modulus Material

table 3

Then, we confirmed the thermal resistance of this low Young's Modulus material without any inorganic filler by conducting 288ºC 10 sec. × 2 times of soldering float. Fig. 3 apparently exhibits that after solder float test, the solder migrates between SR and copper trace. As explained earlier, low Young's Modulus material would show deficiency in thermal resistance because of weak cross-linked density.

fig 3

Fig. 3. Surface Observation after Solder Heat Resistance

Until now, we have developed a novel low young’s modulus material without any fillers, which achieves perfect crack resistance but insufficient thermal resistance. In order to improve thermal resistance, we stuck a thermal resistance layer which is composed of resins with high thermal resistance and great toughness onto the low Young's Modulus material layer. Namely, we reveal the development of a novel two-layer SR film which consists of low Young's Modulus layer and thermal resistance layer, the configuration of two-layer SR film is shown in Fig. 4.

fig 4

 Fig. 4. The Composition of Two-Layer Solder Resist Film

The thermal resistance layer is characterized by toughness, strong heat and chemical resistance, which could withstand rigorous high temperature or chemical process. Also the low Young's Modulus layer could decrease stress effectively and suppress cracks occurring. According to this advanced two-layer structure, we can achieve excellent performances, such as high crack resistance, high resolution, satisfactory thermal resistance, extremely low warpage and high reliability at the same time. Next, we evaluated and explored the characteristics of this novel two-layer SR film, respectively.

3. The Characteristics of Two-Layer Solder Resist Film

3.1 Crack Resistance
First, we confirm the Young's Modulus, CTE and crack resistance of this two-layer SR film. The CTE of this advanced two-layer SR film is 66 ppm, Young's Modulus is 2.3G Pa and 0% crack occurrence frequency. This novel SR film demonstrates outstanding crack resistance, although this SR film has high CTE. It suggests that due to the low Young's Modulus layer working as a stress relaxation layer, the deformation between substrate and SR film could be restrained, contributing to superb crack resistance.

Table 4. The Results of Young's Modulus, CTE and Crack Ratio of Two-Layer SR Film

table 4

3.2 Thermal Resistance
To confirm the thermal resistance of this two-layer SR film, we conducted solder float tests and observed no delamination or migration by the cross-section, as shown in Fig. 5. This result obviously indicates that robust thermal resistance is attributed to this two-layer composition. In other words, we enhanced thermal resistance of this low Young's Modulus film successfully by its unique two-layer structure.

fig 5

Fig. 5. Surface and Cross Section Observation after Solder Heat Resistance

3.3 High Resolution
Photolithography resolution of this two-layer SR film without any inorganic filler was evaluated. Designed opening diameter for the SR opening (SRO) was 40 μm, and SEM pictures are shown in Table 5. This SR film, due to the absence of any inorganic filler inhibiting the occurrence of reflecting and scattering, results in exceptional resolution. This two-layer SR film supports smaller SRO than 40µm and is a suitable material for high density applications.

Table 5. The Resolution of Two-Layer SR Film
table 5

3.4 Warpage
Warpage is common in microelectronics processing. Warped substrates and wafers can affect driven performance, reliability and linewidth control in various processing steps. Until now, zero warpage still has been an enormous challenge for traditional photosensitive materials.
To compare the warpage of conventional SR and this new two-layer SR, we coated materials on 5cm × 5cm × 35μm thickness of Copper foils. Warpage of the sample after full curing was evaluated as warp height of the corners.
Fig. 6 indicates that conventional SR show severe substrate warpage on the two corners. In contrast, new two-layer SR exhibited extremely low warpage, which implies small cure shrinkage because of the feature of low Young's Modulus.

fig 6

Fig. 6. Substrate warpage after cure for conventional SR and Two-Layer SR Film

3.5 Biased - Highly Accelerated Stress Test (B-HAST)
The B-HAST is a highly accelerated method of electronic component reliability testing using temperature and humidity as the environmental parameters. Fig. 7 shows the result of the B-HAST for the conventional SR and two-layer SR film with line and space (L/S) of 12um/13um. The Mean Time To Failure (MTTF) of conventional SR is 337.3 hrs and two-layer SR film is 452.4 hrs. It indicates that even with the fine pattern, the two-layer SR film achieved higher electrical reliability than the conventional SR.

fig 7

Fig. 7. Result of B-HAST for conventional SR and Two- Layer SR Film

3.6 Flip-Chip Assembly
In order to compare the crack resistance between conventional SR and newly developed two-layer SR film, the film was laminated onto BGA substrate (substrate dimension is 50 mm x 50 mm), patterned and post cured, and then, flip-chip mounted on a 25 mm x 25 mm dummy chip. Conducting thermal shock test (TST) and observing the number of cracks after 1000 cycles of TST, as shown in Fig. 8 and Fig. 9.

fig 8

Fig. 8. Process Flow of Flip-Chip Assembly

 fig 9Fig. 9. The Test Board Design

The number of cracks after the thermal shock test is shown in Fig. 10. The crack occurrence frequency of the conventional SR is 65%, whereas that of the new two-layer SR film is as low as 4%. Thus, an overwhelmingly higher crack resistance is attained.
fig 10

Fig. 10. Number of Cracks after TST

In this paper, we indicate that the material with low Young's Modulus also could demonstrate excellent crack resistance, due to the benefit of low Young's Modulus. Furthermore, we developed a novel two-layer SR film with low Young's Modulus exhibiting several excellent properties simultaneously, including outstanding crack and thermal resistance, superior resolution, extremely low warpage and high electrical reliability.

In conclusion, the newly developed two-layer SR film with low Young's Modulus is beneficial for the next generation high-density package, especially for the outermost layer of FC-BGA packages and applications that require higher reliability. Moreover, compared to traditional SR, this two-layer SR film show significantly outstanding flexibility, due to the feature of low Young's Modulus. In other words, this two-layer SR film also could have potential application for flexible electronics or rigid flexible electronics.


1. C. H. Yu, L. J. Yen, C. Y. Hsieh, J. S. Hsieh, Victor C. Y. Chang, C. H. Hsieh, C. S. Liu, C. T. Wang, KC Yee and Doug C. H. Yu “High Performance, High Density RDL for Advanced Packaging” IEEE Electronic Components and Technology Conference(2018) pp.587-593
2. Kazuya Okada, Toko Shiina “Novel Photosensitive Solder Resist with High Reliability for Semiconductor Package” J. Photopolym. Sci. Technol., Vol. 28, No. 1, 2015

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Section 6

Treatment of Polymeric Films Used for Printed Electronic Circuits Using Non-Thermal Plasma
Prof Radu Burlica
Faculty of Electrical Engineering, “Gheorghe Asachi” Technical University of Iasi, Romania 

 radu burlica

Radu Burlica
Gheorghe Asachi Technical University of Iasi

This study aims to present the properties of the polymeric films after being subjected to Dielectric Barrier Discharge (DBD) plasma treatment in atmospheric conditions. Three different commercial films of polyester (Xerox Inkjet transparencies and Autostat CUS5 Clear film) and polycarbonate (Lexan™ 8010 MC) have been considered for the tests. The surface wettability has been evaluated based on static water contact angle (WCA) for different treatment times varying between 0.2 s and 30 s. For the considered materials, the results revealed that the plasma treatment results in changes of the surfaces indicating an increase in surface roughness.

Polymer films have been frequently used in many modern industrial applications owing to their high performance. In the area of printed electronics, polymeric materials such as polycarbonate (PC), polyethylene terephthalate (PET) and other films are used as a substrate material for the manufacture of organic light-emitting diodes, sensor applications and organic solar cells due to their outstanding flexibility, transparency, fold resistance, tensile strength and chemical and corrosion resistance, low weight and lower cost. The manufacture of printed flexible electronics often requires changing the surface of the polymer to improve adhesion or wetting. In this regard, although low-pressure plasma can be used, it was found that atmospheric plasma treatment is more convenient, relatively simple and economical in terms of technology without any vacuum systems suitable for this task. By using an atmospheric pressure reactor, microscopic structures could be more easily formed on the film substrates through in-line or roll-to-roll processing.

The term “plasma” refers to a partially or fully ionized gas composed essentially of free photons, ions and electrons, as well as atoms in their ground or excited states having a neutral charge. These excited and ionized particles carry enough energy to induce chemical reactions at the interface with solid surfaces that change the properties of materials. A DBD reactor has several advantages such as the flexibility of the design and parameters used, the simple setup, low costs and safety in operation.

The DBD reactor has proven its ability to modify different substrates such as metal materials, wood or MDF boards, various polymeric materials used in the textile, food or electronics industries. Many studies conducted in recent years have shown that treatment by means of an air DBD reactor at atmospheric pressure improves the properties of hydrophilicity, increases the surface tension of polymers, also changing the roughness of their substrates, and has the advantage of uniform and fast treatment of the entire surface.

Polyethylene terephthalate (PET) polyester film has been used in a wide range of applications (packaging, printing, capacitors) because it has some good properties and is easy to recycle. It has a comparatively lower cost which make it very popular despite its inadequate wettability and adhesion properties. Additionally, polycarbonate (PC) has high creep resistance, durability, high hardness and excellent optical transparency, being an attractive polymer. PC is used in a variety of applications such as a substitute for glass. However, the adhesive strength between a deposited film and the PC substrate is weak due to the low surface energy. Therefore, in order to increase the surface tension, these materials can be activated by DBD non-thermal plasma treatment.

The main idea of this study is to present the results obtained from DBD treatment of three commercially available polymeric substrate surfaces: Xerox inkjet (polyester), Autostat (polyester) and Lexan (polycarbonate). The materials have been exposed to an air DBD plasma at atmospheric pressure with the aim of modifying the water contact angle (WCA), the adhesion force and the surface morphology.

The two films tested that are relevant to electronics manufacturing are:
1.Lexan™ 8010 MC (polycarbonate). It has a polished surface and high clarity, being usually used in applications relating to electronics, automotive interiors or general electrical appliances.
2.Autostat (polyester film) of the type CUS5 Clear, (untreated, 125 micron) has also been assessed. Autostat is used for the manufacture of membrane and conventional switch circuitry layers such as computer keyboards.

As the non-thermal plasma treatment effect of the considered film surfaces is not constant over time and there are differences depending on the treatment time, it is important to establish how wettability changes with the treatment time, the storage time and the oxidation ageing of these treatments.

Industrial plasma treatments involve continuous and rapid treatment surfaces of large quantities of samples. The diminution of treatment time of such individual samples by a few milliseconds can finally result in the reduction in treatment time of thousands of samples by a few minutes. The primary objective of this study is to determine the optimal treatment time of a polymer surface, which is thus very important for industry.

The dielectric barrier discharges (DBD) were generated in atmospheric air using a reactor with a dielectric between the two circular 60 mm diameter plane electrodes, E1 and E2, respectively, which is covered by a glass plate forming a 3 mm thick dielectric barrier. The distance between the electrodes is 7 mm. The schematic diagram and the image of the non-thermal plasma discharge are shown in Figure 1a,b, respectively. Non-thermal plasma is generated using a high voltage power supply (HVPS) which generates about 20 kHz, an output voltage of 7 kV, the average power per discharge being 40 W, for a 6 mA current.

The polymer layer is placed at a 4 mm distance from E1 electrode. When the voltage applied exceeds the electrical breakdown threshold, an avalanche ionization phenomenon initiates. Due to this phenomenon, a multitude of plasma streamers occur between the electrode and the dielectric glass. The discharge stops when the voltage passes to zero and re-initiates when the voltage changes the polarity.

The use of the dielectric barrier prohibits the evolution of the electric discharge into electric arc. At the same time, the charge carriers accumulated at the dielectric surface, quenches the discharge by lowering the field strength. In the discharge, there are many streams exhibiting concurrently and individually, with a lifespan in the range of nanoseconds.

image 1

Figure 1a: DBD Reactor Schematic Diagram

image 2Figure 1b: DBD Discharge Streams

Water Contact Angle

Sessile drop method is a common technique used for flat surfaces allowing water contact angles to be measured from the drop profile. In the present paper, the authors used an Ossila Contact Angle Goniometer to assess the WCA and the surface free energy of liquid droplets. A calibrated distilled water drop is settled on the polymer surface using a 25 µL syringe provided with a blunt needle (Φ = 0.47 mm). Figure 2 shows the WCA after 30 s of DBD treatment for the Autostat foil, highlighting hydrophilic enhanced properties.

image 5b

Figure 2: The WCA for the treated Autostat foil decreased from 71.2◦ down to 19.5◦.

There are many factors affecting the WCA including impurities, porosity, surface roughness, or surface free energy. The correlation between the water surface tension and the substrate surface energy is described by Young’s Equation (1) where γsv, γsl, γlv and θ are the interfacial tensions of the solid-liquid, solid–vapor, liquid-vapor interfaces and the Young’s contact angle, respectively:

equationEquation (1)

According to Equation (1), when the contact angle is less than 90◦ the surface is hydrophilic while for a contact angle higher than 90◦ the surface is hydrophobic.

The time evolution of the water contact angle (WCA) on the polymeric surface, for different plasma treatment time spans, has been studied.

Contact angle measurement is a relevant method to identify the hydrophilicity of polymeric surfaces. The adhesion of a surface is related to its wetting. To assess the surface wetting, contact angle measurement may be performed for a liquid droplet in contact with a solid surface.


image 5d

Figure 3: The comparison between the immediate effect of plasma treatment on the water contact angle in the case of the tested substrates.

There are no important differences concerning the WCA values obtained after the plasma treatment between the different treatment times considered (from 0.2 up to 5 s). The WCA measurements indicate an important increase of contact angle over time, just after DBD treatment.

This aspect implies that the treated foil must be used immediately after treatment for the best physical wetting property. After 24 h of storage from plasma application, the WCA values increase up to 45◦ while remaining relatively stable even for more than 70 h of storage. 

Adhesion force of coatings applied to the materials has also been assessed together with surface profile analysis. This is beyond the scope of this publication and can be referenced below.

The present study emphasizes a significant decrease in WCA of non-thermal plasma treated polymer film surfaces (around 50% from initial WCA) for all film types considered after only 0.2–0.5 s. This aspect is important for the treatment of the foils used in in-line printing systems where the speeds of the foil movement are very high. Another important factor is the stabilization of the WCA 24 h after the treatment with non-thermal plasma, which is a useful piece of information in the case where the printing is performed after a longer time after the treatment (or in another location) or for the storage of the treated foils.

This paper was originally published by MPDI and can be accessed here 

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Section 7

Automation & the Journey to your Smart Factory
Happy Holden


In Sept and Oct 2022 the ICT held a a series of on-line engineering sessions featuring Happy Holden. They were based on his book "Essential Skills for Engineers" This series of presentations is available now and is free to members and guests. Just register your email below to take you to the link page of the stored webinars.

Happy Holden is a retired electronics manufacturing technologist of international repute, He is a contributing Technical Editor to I-Connect007 and Hon Fellow of the ICT

There are eight on-line sessions of 60 minutes. The following webinars are available and can be accessed individually or part of a complete training course.


a. Introduction and elements of the Journey!  Getting started - The hardest step.
b. Skills - 1 Total Quality Control, Six Sigma, and Statistical Tools, Problem Solving, Design of Experiments \ Predictive Analysis.
c. Skills - 2 Benchmarking, Product and Process Life Cycles, Engineering Economics, Roadmapping.
d. Defining Automation & Automation Methodology Computer Integrated Manufacturing, Automation Strategy and Planning, Process Workstation Analysis.
e. The Smart Factory Networks and Communications, Factory Communication Standards, Digitisation for the Smart Factory.
f. Sensors & chemical analysis Application of Sensors, Automated Analysis, Chemical Control and Regeneration.
g. Skills - 3 Figure of Merit / Shared Vision, Metrics and Dimensional Analysis, Lean Manufacturing.


Quality Functional Deployment and House of Quality, Predictive Engineering, On-Line Instruction and Distance Learning.
i. Software Driven Automation As part of the ICT Engineering Training sessions, we continued the theme with a webinar from Michael Ford of Aegis - Software Driven Automation with an introduction by Pete Starkey.

 Enter your email here to link to the video gallery

Follow this link for further details.

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Section 8  ICT Seminar and AGM 7th March 2023


RexRozarioHonararyFellowship2Rex Rozario
Hon Fellow

Widely believed to be the traditional Centre of England, Meriden was a popular venue for a gathering of the UK printed circuit community this month. They braved the forecast of heavy snow for the Institute of Circuit Technology’s annual general meeting to learn about current developments and challenges in a thought-provoking technical seminar and to network with industry peers and contemporaries. Thankfully, the forecasted heavy snowfall did not reach Meriden until after the event; we only had a few flurries, although the weather caused considerable disruption elsewhere in the country.

After the formal business of the annual general meeting had been efficiently managed and conducted by ICT Chair Emma Hudson, the early highlight of the evening session was the award of Honorary Fellowship to Rex Rozario OBE. He is credited with being part of the team that developed the first circuit board in England in the 1950s.

 Alun Morgan2Alun Morgan

The State of Energy
Technical director Bill Wilkie introduced and moderated the seminar program. Alun Morgan, president of EIPC, was the first speaker and brought his views on energy, both in general and in the real-world situation.

The increasing availability of energy has transformed the course of humanity, he said, and the quantity consumed and produced has inevitably continued to increase. Fossil fuels have been supplemented with new energy sources: hydropower, nuclear and more recently with renewable technologies. Although decarbonisation is progressing slowly, it is essential that fossil fuels be displaced in the energy mix at a much faster rate.

His charts of global energy consumption and energy production by fuel type illustrated the wide gap that exist between:

Groups of principal sources: oil, coal, and gas
Groups of alternatives: biofuel, solar, wind, nuclear, hydropower, etc.
The challenge is in determining how to bridge that gap if the use of oil, coal, and gas are progressively discontinued. Neither solar nor hydro alone will be sufficient, and Morgan highlighted the example of nuclear power as adopted by France, where it has been calculated that the release of over 30 billion tons of CO2 emissions has been avoided, and the principal remaining source of air pollution is motor vehicles. The current area of interest is in small and simpler units for generating electricity and process heat from nuclear power, driven by the need to reduce capital costs and to avoid large grid systems. Morgan remarked that numerous technologies are involved; he mentioned the development of Generation 4 nuclear reactors based on Uranium 238, of which there is an abundant supply, and that is expected to be in service commercially around 2030.

Morgan then focused on the PCB industry, reviewing world trends and concluding with Europe’s position. Whereas world PCB production has grown from $33.1 billion in 2000 to $60.8 billion in 2019, Europe’s share has reduced from $5.4 billion to $1.9 billion during the same period. But although the number of manufacturers has shrunk from 550 to 173, revenues have remained relatively stable since 2010. The European PCB industry is losing ground due to raw materials and equipment being increasingly difficult to source in Europe, reduced investment capital compared with other regions, and reduced availability of technical resources and workforce. The relative stability of the industry is closely related to its areas of specialisation: strong defence and aeronautics sectors, strong medical sector, and other specialised areas. Presently, the top 30 companies made 70% of the volume in Europe. But the industry was heavily dependent on its supply chain and needed to maintain its critical mass to secure supply continuity.

Returning to Morgan’s primary topic, the unique competitive disadvantage Europe suffers relative to its competitors is the cost of energy. In 2021, even before Russia invaded Ukraine, the average price of electricity in U.S. dollars per kilowatt hour was $0.323 in Germany compared with $0.109 in the U.S. and $0.084 in China.

In seeking government support, current employment numbers in the PCB industry are not large enough to have meaningful political significance, but defence and security considerations certainly are—a stable European supply base is considered essential—and it is from this perspective that government is being approached.


ProfAndyCobleyAndy Cobley

A Focus on Assistive Device Technology
Coventry University continues to collaborate in a wide range of international research and innovation programs, and has acted as coordinator for the Maturolife assistive technology project aimed at providing older people with security to enable them to live independently. Existing alarms and tracking devices designed to alert carers to falls or a person’s location are often unsightly, stigmatising the user and resulting in high abandonment rates. The interdisciplinary Maturolife research team includes creative artists and fashion designers as well as specialists in nanotechnology, electrochemistry, and materials science, to integrate electronics and sensors into fabrics and textiles while achieving a balance between aesthetics and functionality. Professor Andy Cobley reported the development of a selective metallisation technique for depositing electroless copper to fully encapsulate individual fibres in textile materials. The outcome is a fabric with normal feel and drape, selectively conductive but with no metal wires.

A key component of the process is an ink-jettable copper-silver core shell catalyst. This is an alternative to palladium which, although an excellent catalyst, was very expensive and classified as a “critical raw material.” Pure copper nanoparticle colloids are not stable and tend to aggregate over time. Using polyacrylic acid as a shell-ligand produces a stable colloid which enables a uniform electroless copper deposit, but the long-term stability of the ink needs improvement. Adding silver nitrate to a copper nanoparticle/polyacrylic acid dispersion results in an exchange reaction, creating a silver-core shell colloid. This is formulated into an ink-jet printable catalyst, and the silver shell significantly increased the lifetime of the ink. Printed onto a polyester fabric, this ink enables selective metallisation with electroless copper and increasing the number of print cycles increases the copper mass gain. It has been observed that the resistance of the copper deposit decreases with increasing print cycles, there is some difference between warp and weft directions, and resistance increases after each washing cycle.

Professor Cobley showed examples of Maturolife prototypes incorporated into assistive footwear, designed to help in the understanding of gait and balance.


Robert ArtRobert Art 

Things to Consider When It Comes to Thermals
Robert Art, global account manager, IMS, with Ventec International Group, who gave valuable, practical advice on the choice and specification of materials for thermal management applications, explaining the terminology, the true significance of datasheet values, and the reasons why different test methods give different results. What does the OEM really want? What are the significant parameters? Does the designer understand what he is specifying? Is the fabricator instructed to use a more expensive material than necessary to fulfil the performance requirement? Art provided authoritative answers.

He began by reviewing the nature and basic construction of insulated metal substrates and their important datasheet parameters: thermal resistor, thermal impedance, thermal conductivity, glass transition temperature, maximal operating temperature, breakdown voltage and hi-pot withstand.

The first and most important datasheet value he considered was thermal resistor or thermal impedance, denoted Rth or Zth, which was measured directly and from which thermal conductivity was calculated. Different test methods gave different values; in the example he used, ISO 22007-2 gave 5W/mK, ASTM E1461 gave 3.3W/mK, ASTM D5470 gave 3.0W/mK, and Bruggeman Modelling gave 12W/mK. Art commented that the ASTM D5470 test was most commonly used; it gave the lowest value because it measured the complete stackup, including the losses in the transfer areas.

“Don’t accept thermal conductivity values,” he advised, and demonstrated the sizeable tolerance bands associated with different test methods, implying that a low-cost competitor can quote almost any value and still be in tolerance, depending on the method.

Art commented that Ventec is a member of an IPC working group that includes other suppliers and ZFR (Zentrum fuer Waermemanagement) in Stuttgart, to improve the accuracy of the measurement method by tightening thickness tolerances and clearly defining test parameters and probe locations.

He asked, “When should you take a deeper look to the datasheet?” and then listed some key points. These include checking which test method has been used for dielectrics with claimed thermal conductivity of 4W/mK and higher, checking in detail how Rth has been measured, and with what tolerance. For values below 0.4, it’s checking the dielectric thickness that has been used as a probe for an ASTM test, questioning why different thermal measurement methods have been used for closely related values quoted on the datasheet in order to improve their appearance, and being suspicious of remarks like “modified” in reference to test methods.

Having briefly discussed maximal operating temperature, breakdown voltage and hi-pot withstand, Art mentioned the significance of glass transition temperature in IMS dielectrics compared with rigid laminates, where a lower Tg gave a more resilient product and in combination with a low-expansion aluminium alloy helped to mitigate solder joint cracking.

But his over-riding message in specifying an IMS material was, “Be careful, and make sure you understand how it is measured.”


 Chris WallChris Wall


Chemical Legislation and Restrictions on Solder Masks

The final presentation of the seminar came from Chris Wall, technical director of Electra Polymers, who succeeded in making the subject of chemical legislation and restrictions on solder masks both interesting and enlightening. He explained that the European Union REACH regulation (Registration, Evaluation, Authorisation, and Restriction of Chemicals), which originally came into force in 2007, requires manufacturers and importers of chemicals to register the substances they produce or place on the market in Europe with the European Chemicals Agency (ECHA). The REACH regulation establishes a process for identifying and controlling substances of very high concern (SVHCs). When the UK withdrew from the European Union, the UK government created UK REACH, which adopted all the provisions of REACH (as they were BREXIT at the time) and regulates chemicals placed on the market in the UK. The UK REACH and the EU REACH regulations operate independently of each other and suppliers must ensure that they comply with both regulations where necessary. Clearly, this raises potential issues for global suppliers.

Wall pointed out that, currently, the specific relevance to solder mask formulation is to the widely-used photoinitiators “907” (2-methyl-1-(4-methylthiophenyl)-2-morpholinopropan-1-one) and “369” (2-benzyl-2-dimethylamino-4'-morpholinobutyrophenone). Both materials have recently been prioritised for inclusion in the Authorisation List of substances that can only be used under specific conditions, such that the risks are adequately controlled. Certain other components of solder masks are subject to, or likely to become subject to, usage restrictions.

The timeline for photoinitiators “907” and “369” is an Authorisation Period of 18, 21, or 24 months from the date of inclusion in the Authorisation List, for manufacturers or importers to apply for authorisation to continue manufacture of import of the material. If this is granted, it will be authorised for use for a further period of time. At the same time, a “Sunset Date” will be notified, which is 18 months after the “Latest Application Date. After the “Sunset Date,” the substance can no longer be used or placed on the market without an authorisation.

Wall’s presentation raised many questions from the audience, to which he responded reassuringly, stressing that there is no immediate need to panic, and that Electra and its counterparts in the industry have been working hard to develop liquid photoimageable solder mask formulations of equivalent performance which do not contain the “907” or “369” ingredients.

 Bill WilkieBill Wilkie

Bill Wilkie brought the formal proceedings to a close, with warm thanks to all who braved the weather forecast to participate, and wished everyone a safe journey home through the snow.

Note: Much thanks to Alun Morgan for the beautiful images.

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Section 9

Members News


Honorary Fellows

The following members have been awarded Honorary Fellowship grading in recognition of their contribution to our industry and the ICT. They all have an outstanding reputation and it is fitting that the The Institute is able to show gratitude to them by awarding them this status.

David Burling
Terry Boby
Martin Cotton
Jim Douglas
Russell Gregory
Derek Groves
Steve Jones
Phil Leader
Bihari Patel
Rex Rozario
Andy Williams
David Woodley

Bill Wilkie – Membership Secretary – March 2023

john rankinJohn Rankin

This year we say thankyou to John Rankin, who began PCB life at Bepi and was training manager before joining Morton. John has given the photomechanical processes lecture since 2005 and is now retiring. John has been presented with an inscribed Pewter Tankard in recognition of his help and dedication to the Foundation Course.

rankin tankard

Presented to


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Section 10

Industry News

A-Gas Electronic Materials

A-Gas EM Gold Investors in People Award
A-Gas Electronic Materials is pleased to announce it has been accredited with the GOLD Investors in People award. Thank you to all of the employees for all their hard work in achieving this amazing standard. Read more... 

 Electra Polymers The Impact of REACH
Pete Starkey and Ashley Steers of Electra Polymers Ltd discuss SVHC, REACH and changes to solder mask processes and products.  Read more...
GSPK Circuits Power Electronics Busbars
GSPK is the leading manufacturer for Heavy Copper PCBs for Power Electronics. It is not uncommon for a customer to ask us to manufacture a 70oz PCB with inner layers to 15oz. We can embed copper so that even with mix copper weights the outer layer will have a smooth planar finish. Read more...
 Merlin Circuit Technology Merlin Circuit Technology Ltd – NADCAP RE-Approval
Merlin Circuit Technology Limited are very happy to announce that we have been re-approved for the NADCAP Accreditation. This is excellent news for Merlin and highlights the dedication of our staff at all levels within the company – working as a team to again achieve this Internationally recognised accreditation. Read more...
Newbury Electronics Sponsors of Southampton University Formula Student Team
We are very pleased to announce that Newbury Electronics Ltd are sponsors of Southampton University Formula Student Team for 2023. Thanks to our fast turnaround manufacture of their PCB designs they have been able to accelerate their electronics development and start manufacturing their 2023 vehicle.  Read more...

New Partnership for Taiyo Circuit Automation and Viking Test Ltd.
Viking Test Ltd are now Taiyo Circuit Automation’s distributor for India and the UK. Taiyo Circuit Automation have announced a new partnership with Viking Test Ltd.
This partnership is part of the ongoing strategy to increase technical and sales support for Taiyo Circuit Automation’s range of coaters and ovens operating in the Indian and UK regions. Read more...

Trackwise Designs  Length-unlimited Flexible Circuits Inspire Diverse New Applications
Trackwise Designs plc has revealed that its length-unlimited flexible printed circuits (FPCs) are driving product innovation in many sectors including agritech, wearables, industrial sensing and heating elements. As design engineers apply the Trackwise-patented Improved Harness Technology™ to solve their design challenges and enable smarter and more advanced products. Read more...
Ventec International High Thermal Conductive Metal Base Laminate
Ventec are pleased to announce the launch of its latest high thermal conductive metal base laminate VT-4BC designed for use in applications requiring excellent performance in thermal management including super bright lighting, power modules, controllers, motor drives and rectifiers. Read more...
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Section 11

Membership News 

bill wilkie
Bill Wilkie
Technical Director and Membership Secretary, Institute of Circuit Technology


New Corporate Members
Schmoll Mashinen gmbh
A-gas Electronics
MacDermid Alpha
Pillarhouse International

New Members
10597 Nagaraj U – Micropack India – Associate
10598 Pratish Patel – EI Connect – Member
10599 Paul Lindsay – Macdermid Alpha – Member

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Section 12 Corporate Members of the ICT  
Adeon Technologies BV adeon corp
A-Gas Electronic Materials a gas
Amphenol Invotec Ltd invotec corp
Atotech UK Ltd. atotech corp
CCE Europe cce corp
CCI Eurolam cci eurolam corp
Electra Polymers Ltd electra corp
The Eurotech Group  eurotech corp
Exception PCB Solutions  exception corp
Faraday Printed Circuits Ltd faraday corp
Graphic plc graphic corp 
GSPK (TCL Group) gspk corp 
Macdermid Alpha macdermid alpha
HMGCC hmgcc corp
Holders Technology UK holders tech2 corp
Jiva Materials jiva
Merlin Circuit Technology Ltd merlin corp
Merlin Flex Ltd merlin corp
Minnitron Ltd minitron corp
Newbury Electronics Ltd newbury corp
Photomechanical Services photomech corp
Pillarhouse International pillarhouse
PMD pmd corp www.pmdchemicals
Polar Instruments Polar
Schmoll Maschinen schmoll
Stevenage Circuits Ltd stevenage corp 
Strip Tinning Ltd strip tinning
Taiyo America, Inc taiyo
Trackwise Designs Ltd trackwise corp
Ventec Europe ventec corp
Zot Engineering Ltd zot corp 
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Section 13

ICT Council Members

Council Members

Emma Hudson (Chair), Andy Cobley (Past Chairman), Steve Payne (Hon Deputy Chairman), Chris Wall (Treasurer), William Wilkie (Technical Director, Hon Sec, Membership & Events), Richard Wood-Roe (Journal Editor & Web Site),  Jim Francey, Martin Goosey, Lynn Houghton, Pete Starkey, Francesca Stern and Bob Willis, 

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Section 14

Editors Notes

The ICT Journal


Richard Wood-Roe
Journal Editor

Instructions / Hints for Contributors

1. As it is a digital format the length is not an issue. Short is better than none at all!

2. Article can be a paper or a text version of a seminar or company presentation. Please include data tables, graphs, or powerpoint slides. We can shrink them down to about quarter of a page. Obviously not just bullet points to speak from.

3. Photo's are welcome.

4. We would not need  source cross references

5. Title of presentation - Of course! Date, Job title of Author and Company represented.

6. An introductory summary of about 150 words would give the reader a flavour of what it's all about.

7. Style - we don't want out and out advertising but we do recognise that the author has a specialism in the product or process that will include some trade promotion. Sometimes it will be a unique process or equipment so trade specific must be allowed.

8. Date and any info relating to where or if this article may have been published before.

9. We can accept virtually any format. Word, Powerpoint, publisher, PDF or Open Office equivalents. 

10. Also, to make it easy, the author can provide a word file to go along with his original powerpoint presentation and I/we can merge it together and select the required images. 

11. A photo of author or collaborators.

I really do look forward to receiving articles for publication.

Richard Wood-Roe

This email address is being protected from spambots. You need JavaScript enabled to view it.

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